[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.

The PowerISA 3.0 defines some instructions (such as LXV and STXV) that take a displacement as a quad-word offset (i.e. the effective address is calculated by shifting the value left by 4). As a convenience and consistency with DS-Form instructions, the assembler takes a byte offset. So it is meaningless for a byte offset to not be a multiple of 16.
The assembler already complains when assembling these instructions with an incorrect displacement, we just need to make sure we don't emit them this way.

This patch also fixes https://bugs.llvm.org/show_bug.cgi?id=33671.


Repository:
  rL LLVM

https://reviews.llvm.org/D35007

Files:
  lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/PR33671.ll
  test/CodeGen/PowerPC/build-vector-tests.ll
  test/CodeGen/PowerPC/ppc64-i128-abi.ll
  test/CodeGen/PowerPC/swaps-le-6.ll
  test/CodeGen/PowerPC/vsx-p9.ll

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