[PATCH] D34240: [WebAssembly] Expansion of llvm.umul.overflow with i64 type operands.

[Jatin Bhateja via Phabricator via llvm-commits]

jbhateja updated this revision to Diff 105212.
jbhateja added a comment.

[X86] Improvement in CodeGen instruction selection for LEAs

  1/  Operand folding during complex pattern matching for LEAs has been
      extended to such that it promotes Scale to accommodate similar operand
      appearing in the DAG.
      e.g.
            T1 = A + B
            T2 = T1 + 10
            T3 = T2 + A
      For above DAG rooted at T3, X86AddressMode will no look like
            Base = B , Index = A , Scale = 2 , Disp = 10
  
  2/  During OptimizeLEAPass down the pipeline CSE will now be performed over LEAs
      so that if there is an opportunity then complex LEAs (having 3 operands)
      could be factored out.
      e.g.
           leal 1(%rax,%rcx,1), %rdx
           leal 1(%rax,%rcx,2), %rcx
      will be factored as following
           leal 1(%rax,%rcx,1), %rdx
           leal (%rdx,%rcx)   , %edx


https://reviews.llvm.org/D34240

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86OptimizeLEAs.cpp
  test/CodeGen/WebAssembly/umulo-i64.ll
  test/CodeGen/X86/lea-opt-cse.ll
  test/CodeGen/X86/mul-constant-i16.ll
  test/CodeGen/X86/mul-constant-i32.ll
  test/CodeGen/X86/mul-constant-i64.ll
  test/CodeGen/X86/mul-constant-result.ll
  test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
  utils/TableGen/DAGISelMatcherGen.cpp

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