[PATCH] D34394: [MachineVerifier] Add check that tied physregs aren't different.
Jesper Antonsson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 3 07:34:19 PDT 2017
JesperAntonsson updated this revision to Diff 105049.
JesperAntonsson added a comment.
Added a MIR test for the check. Thanks to Quentin for input.
https://reviews.llvm.org/D34394
Files:
lib/CodeGen/MachineVerifier.cpp
test/CodeGen/MIR/X86/tied-physical-regs-match.mir
Index: test/CodeGen/MIR/X86/tied-physical-regs-match.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/X86/tied-physical-regs-match.mir
@@ -0,0 +1,22 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the Machine Verifier detects tied physical registers
+# that doesn't match.
+
+--- |
+
+ define i32 @foo() {
+ entry:
+ ret i32 0
+ }
+
+...
+---
+name: foo
+body: |
+ bb.0.entry:
+ liveins: %rdi
+
+ ; CHECK: Tied physical registers must match.
+ %rbx = AND64rm killed %rdx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags
+ RETQ %rbx
+...
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -985,6 +985,14 @@
report("Operand should be tied", MO, MONum);
else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
report("Tied def doesn't match MCInstrDesc", MO, MONum);
+ else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
+ const MachineOperand &MOTied = MI->getOperand(TiedTo);
+ if (!MOTied.isReg())
+ report("Tied counterpart must be a register", &MOTied, TiedTo);
+ else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
+ MO->getReg() != MOTied.getReg())
+ report("Tied physical registers must match.", &MOTied, TiedTo);
+ }
} else if (MO->isReg() && MO->isTied())
report("Explicit operand should not be tied", MO, MONum);
} else {
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