[PATCH] D34276: [mips] Alter register classes for MSA pseudo f16 instructions

[Stefan Maksimovic via Phabricator via llvm-commits]

smaksimovic updated this revision to Diff 105048.
smaksimovic added a comment.

- Moved virtual registers inside if blocks
- Introduced mtc1/mfc1 counterparts which use FGR64Opnd since copies between FGR32 and FGR64 register classes cannot be performed




https://reviews.llvm.org/D34276

Files:
  lib/Target/Mips/MipsInstrFPU.td
  lib/Target/Mips/MipsSEISelLowering.cpp
  test/CodeGen/Mips/msa/f16-llvm-ir.ll

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