[llvm] r306971 - [GlobalISel][X86] Support vector type G_UNMERGE_VALUES selection.
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 2 01:15:49 PDT 2017
Author: ibreger
Date: Sun Jul 2 01:15:49 2017
New Revision: 306971
URL: http://llvm.org/viewvc/llvm-project?rev=306971&view=rev
Log:
[GlobalISel][X86] Support vector type G_UNMERGE_VALUES selection.
Summary:
Support vector type G_UNMERGE_VALUES selection.
For now G_UNMERGE_VALUES marked as legal for any type, so nothing to do in legalizer.
Reviewers: t.p.northover, qcolombet, zvi, guyblank
Reviewed By: guyblank
Subscribers: rovka, kristof.beyls, guyblank, llvm-commits
Differential Revision: https://reviews.llvm.org/D33665
Added:
llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
Modified:
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/test/CodeGen/X86/GlobalISel/add-vec.ll
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=306971&r1=306970&r2=306971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Sun Jul 2 01:15:49 2017
@@ -75,6 +75,8 @@ private:
bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
+ bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
+ MachineFunction &MF) const;
bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
@@ -272,6 +274,8 @@ bool X86InstructionSelector::select(Mach
return true;
if (selectUadde(I, MRI, MF))
return true;
+ if (selectUnmergeValues(I, MRI, MF))
+ return true;
if (selectMergeValues(I, MRI, MF))
return true;
if (selectExtract(I, MRI, MF))
@@ -918,6 +922,33 @@ bool X86InstructionSelector::selectInser
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
+bool X86InstructionSelector::selectUnmergeValues(MachineInstr &I,
+ MachineRegisterInfo &MRI,
+ MachineFunction &MF) const {
+ if (I.getOpcode() != TargetOpcode::G_UNMERGE_VALUES)
+ return false;
+
+ // Split to extracts.
+ unsigned NumDefs = I.getNumOperands() - 1;
+ unsigned SrcReg = I.getOperand(NumDefs).getReg();
+ unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
+
+ for (unsigned Idx = 0; Idx < NumDefs; ++Idx) {
+
+ MachineInstr &ExtrInst =
+ *BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
+ .addReg(SrcReg)
+ .addImm(Idx * DefSize);
+
+ if (!select(ExtrInst))
+ return false;
+ }
+
+ I.eraseFromParent();
+ return true;
+}
+
bool X86InstructionSelector::selectMergeValues(MachineInstr &I,
MachineRegisterInfo &MRI,
MachineFunction &MF) const {
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/add-vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/add-vec.ll?rev=306971&r1=306970&r2=306971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/add-vec.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/add-vec.ll Sun Jul 2 01:15:49 2017
@@ -1,38 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=SKX
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=core-avx2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=corei7-avx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
+
define <16 x i8> @test_add_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) {
-; SKX-LABEL: test_add_v16i8:
-; SKX: # BB#0:
-; SKX-NEXT: vpaddb %xmm1, %xmm0, %xmm0
-; SKX-NEXT: retq
+; ALL-LABEL: test_add_v16i8:
+; ALL: # BB#0:
+; ALL-NEXT: vpaddb %xmm1, %xmm0, %xmm0
+; ALL-NEXT: retq
%ret = add <16 x i8> %arg1, %arg2
ret <16 x i8> %ret
}
define <8 x i16> @test_add_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) {
-; SKX-LABEL: test_add_v8i16:
-; SKX: # BB#0:
-; SKX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
-; SKX-NEXT: retq
+; ALL-LABEL: test_add_v8i16:
+; ALL: # BB#0:
+; ALL-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; ALL-NEXT: retq
%ret = add <8 x i16> %arg1, %arg2
ret <8 x i16> %ret
}
define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
-; SKX-LABEL: test_add_v4i32:
-; SKX: # BB#0:
-; SKX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; SKX-NEXT: retq
+; ALL-LABEL: test_add_v4i32:
+; ALL: # BB#0:
+; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; ALL-NEXT: retq
%ret = add <4 x i32> %arg1, %arg2
ret <4 x i32> %ret
}
define <2 x i64> @test_add_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) {
-; SKX-LABEL: test_add_v2i64:
-; SKX: # BB#0:
-; SKX-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; SKX-NEXT: retq
+; ALL-LABEL: test_add_v2i64:
+; ALL: # BB#0:
+; ALL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; ALL-NEXT: retq
%ret = add <2 x i64> %arg1, %arg2
ret <2 x i64> %ret
}
@@ -42,6 +45,20 @@ define <32 x i8> @test_add_v32i8(<32 x i
; SKX: # BB#0:
; SKX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v32i8:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v32i8:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
%ret = add <32 x i8> %arg1, %arg2
ret <32 x i8> %ret
}
@@ -51,6 +68,20 @@ define <16 x i16> @test_add_v16i16(<16 x
; SKX: # BB#0:
; SKX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v16i16:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v16i16:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpaddw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
%ret = add <16 x i16> %arg1, %arg2
ret <16 x i16> %ret
}
@@ -60,6 +91,20 @@ define <8 x i32> @test_add_v8i32(<8 x i3
; SKX: # BB#0:
; SKX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v8i32:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v8i32:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
%ret = add <8 x i32> %arg1, %arg2
ret <8 x i32> %ret
}
@@ -69,6 +114,20 @@ define <4 x i64> @test_add_v4i64(<4 x i6
; SKX: # BB#0:
; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v4i64:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v4i64:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpaddq %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
%ret = add <4 x i64> %arg1, %arg2
ret <4 x i64> %ret
}
@@ -78,6 +137,26 @@ define <64 x i8> @test_add_v64i8(<64 x i
; SKX: # BB#0:
; SKX-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v64i8:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v64i8:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
+; AVX1-NEXT: vpaddb %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
+; AVX1-NEXT: vpaddb %xmm6, %xmm5, %xmm5
+; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
+; AVX1-NEXT: retq
%ret = add <64 x i8> %arg1, %arg2
ret <64 x i8> %ret
}
@@ -87,6 +166,26 @@ define <32 x i16> @test_add_v32i16(<32 x
; SKX: # BB#0:
; SKX-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v32i16:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v32i16:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
+; AVX1-NEXT: vpaddw %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
+; AVX1-NEXT: vpaddw %xmm6, %xmm5, %xmm5
+; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpaddw %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
+; AVX1-NEXT: retq
%ret = add <32 x i16> %arg1, %arg2
ret <32 x i16> %ret
}
@@ -96,6 +195,26 @@ define <16 x i32> @test_add_v16i32(<16 x
; SKX: # BB#0:
; SKX-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v16i32:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v16i32:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
+; AVX1-NEXT: vpaddd %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
+; AVX1-NEXT: vpaddd %xmm6, %xmm5, %xmm5
+; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
+; AVX1-NEXT: retq
%ret = add <16 x i32> %arg1, %arg2
ret <16 x i32> %ret
}
@@ -105,6 +224,26 @@ define <8 x i64> @test_add_v8i64(<8 x i6
; SKX: # BB#0:
; SKX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq
+;
+; AVX2-LABEL: test_add_v8i64:
+; AVX2: # BB#0:
+; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: retq
+;
+; AVX1-LABEL: test_add_v8i64:
+; AVX1: # BB#0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
+; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
+; AVX1-NEXT: vpaddq %xmm6, %xmm5, %xmm5
+; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
+; AVX1-NEXT: retq
%ret = add <8 x i64> %arg1, %arg2
ret <8 x i64> %ret
}
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir?rev=306971&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir Sun Jul 2 01:15:49 2017
@@ -0,0 +1,53 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
+--- |
+ define void @test_unmerge() {
+ ret void
+ }
+
+...
+---
+name: test_unmerge
+# AVX-LABEL: name: test_unmerge
+#
+# AVX512VL-LABEL: name: test_unmerge
+alignment: 4
+legalized: true
+regBankSelected: true
+# AVX: registers:
+# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
+# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+#
+# AVX512VL: registers:
+# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr }
+ - { id: 1, class: vecr }
+ - { id: 2, class: vecr }
+# AVX: %0 = IMPLICIT_DEF
+# AVX-NEXT: %1 = COPY %0.sub_xmm
+# AVX-NEXT: %2 = VEXTRACTF128rr %0, 1
+# AVX-NEXT: %xmm0 = COPY %1
+# AVX-NEXT: %xmm1 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0, implicit %xmm1
+#
+# AVX512VL: %0 = IMPLICIT_DEF
+# AVX512VL-NEXT: %1 = COPY %0.sub_xmm
+# AVX512VL-NEXT: %2 = VEXTRACTF32x4Z256rr %0, 1
+# AVX512VL-NEXT: %xmm0 = COPY %1
+# AVX512VL-NEXT: %xmm1 = COPY %2
+# AVX512VL-NEXT: RET 0, implicit %xmm0, implicit %xmm1
+body: |
+ bb.1 (%ir-block.0):
+
+ %0(<8 x s32>) = IMPLICIT_DEF
+ %1(<4 x s32>), %2(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
+ %xmm0 = COPY %1(<4 x s32>)
+ %xmm1 = COPY %2(<4 x s32>)
+ RET 0, implicit %xmm0, implicit %xmm1
+
+...
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir?rev=306971&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir Sun Jul 2 01:15:49 2017
@@ -0,0 +1,74 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
+--- |
+ define void @test_unmerge_v128() {
+ ret void
+ }
+
+ define void @test_unmerge_v256() {
+ ret void
+ }
+
+...
+---
+name: test_unmerge_v128
+# ALL-LABEL: name: test_unmerge_v128
+alignment: 4
+legalized: true
+regBankSelected: true
+# ALL: registers:
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# ALL-NEXT: - { id: 3, class: vr128x, preferred-register: '' }
+# ALL-NEXT: - { id: 4, class: vr128x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr }
+ - { id: 1, class: vecr }
+ - { id: 2, class: vecr }
+ - { id: 3, class: vecr }
+ - { id: 4, class: vecr }
+# ALL: %0 = IMPLICIT_DEF
+# ALL-NEXT: %1 = COPY %0.sub_xmm
+# ALL-NEXT: %2 = VEXTRACTF32x4Zrr %0, 1
+# ALL-NEXT: %3 = VEXTRACTF32x4Zrr %0, 2
+# ALL-NEXT: %4 = VEXTRACTF32x4Zrr %0, 3
+# ALL-NEXT: %xmm0 = COPY %1
+# ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+
+ %0(<16 x s32>) = IMPLICIT_DEF
+ %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
+ %xmm0 = COPY %1(<4 x s32>)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_unmerge_v256
+# ALL-LABEL: name: test_unmerge_v256
+alignment: 4
+legalized: true
+regBankSelected: true
+# ALL: registers:
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr }
+ - { id: 1, class: vecr }
+ - { id: 2, class: vecr }
+# ALL: %0 = IMPLICIT_DEF
+# ALL-NEXT: %1 = COPY %0.sub_ymm
+# ALL-NEXT: %2 = VEXTRACTF64x4Zrr %0, 1
+# ALL-NEXT: %xmm0 = COPY %1
+# ALL-NEXT: RET 0, implicit %ymm0
+body: |
+ bb.1 (%ir-block.0):
+
+ %0(<16 x s32>) = IMPLICIT_DEF
+ %1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
+ %xmm0 = COPY %1(<8 x s32>)
+ RET 0, implicit %ymm0
+
+...
+
More information about the llvm-commits
mailing list