[llvm] r306875 - GlobalISel: add G_IMPLICIT_DEF instruction.

Quentin Colombet via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 30 14:09:02 PDT 2017


Hi Tim,

Should we add an actual opcode?
Put differently are we going to treat G_IMPLICIT_DEF and IMPLICIT_DEF differently?

I believe this only gets us the isPreISelxxx helper for “free”. But if that’s the only thing, I would argue we can fix isPreISelxxx to be smarter about those. Anyhow, I think it needs to be discussed.

Cheers,
-Quentin

> On Jun 30, 2017, at 1:27 PM, Tim Northover via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: tnorthover
> Date: Fri Jun 30 13:27:36 2017
> New Revision: 306875
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=306875&view=rev
> Log:
> GlobalISel: add G_IMPLICIT_DEF instruction.
> 
> It looks like there are two target-independent but not GISel instructions that
> need legalization, IMPLICIT_DEF and PHI. These are already anomalies since
> their operands have important LLTs attached, so to make things more uniform it
> seems like a good idea to add generic variants. Starting with G_IMPLICIT_DEF.
> 
> Added:
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
> Modified:
>    llvm/trunk/include/llvm/Target/GenericOpcodes.td
>    llvm/trunk/include/llvm/Target/TargetOpcodes.def
>    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
>    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
>    llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
>    llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
>    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
> 
> Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
> +++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Fri Jun 30 13:27:36 2017
> @@ -49,6 +49,12 @@ def G_TRUNC : Instruction {
>   let hasSideEffects = 0;
> }
> 
> +def G_IMPLICIT_DEF : Instruction {
> +  let OutOperandList = (outs type0:$dst);
> +  let InOperandList = (ins);
> +  let hasSideEffects = 0;
> +}
> +
> def G_FRAME_INDEX : Instruction {
>   let OutOperandList = (outs type0:$dst);
>   let InOperandList = (ins unknown:$src2);
> 
> Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
> +++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Fri Jun 30 13:27:36 2017
> @@ -222,6 +222,8 @@ HANDLE_TARGET_OPCODE(G_OR)
> HANDLE_TARGET_OPCODE(G_XOR)
> 
> 
> +HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
> +
> /// Generic instruction to materialize the address of an alloca or other
> /// stack-based object.
> HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
> 
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Fri Jun 30 13:27:36 2017
> @@ -166,6 +166,20 @@ LegalizerHelper::LegalizeResult Legalize
>   switch (MI.getOpcode()) {
>   default:
>     return UnableToLegalize;
> +  case TargetOpcode::G_IMPLICIT_DEF: {
> +    int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
> +                   NarrowTy.getSizeInBits();
> +
> +    SmallVector<unsigned, 2> DstRegs;
> +    for (int i = 0; i < NumParts; ++i) {
> +      unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
> +      MIRBuilder.buildUndef(Dst);
> +      DstRegs.push_back(Dst);
> +    }
> +    MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
> +    MI.eraseFromParent();
> +    return Legalized;
> +  }
>   case TargetOpcode::G_ADD: {
>     // Expand in terms of carry-setting/consuming G_ADDE instructions.
>     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
> 
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp Fri Jun 30 13:27:36 2017
> @@ -35,6 +35,8 @@
> using namespace llvm;
> 
> LegalizerInfo::LegalizerInfo() {
> +  DefaultActions[TargetOpcode::G_IMPLICIT_DEF] = NarrowScalar;
> +
>   // FIXME: these two can be legalized to the fundamental load/store Jakob
>   // proposed. Once loads & stores are supported.
>   DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
> 
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Fri Jun 30 13:27:36 2017
> @@ -478,7 +478,7 @@ void MachineIRBuilder::buildSequence(uns
> }
> 
> MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) {
> -  return buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Res);
> +  return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res);
> }
> 
> MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
> 
> Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Fri Jun 30 13:27:36 2017
> @@ -39,6 +39,9 @@ AArch64LegalizerInfo::AArch64LegalizerIn
>   const LLT v4s32 = LLT::vector(4, 32);
>   const LLT v2s64 = LLT::vector(2, 64);
> 
> +  for (auto Ty : {p0, s1, s8, s16, s32, s64})
> +    setAction({G_IMPLICIT_DEF, Ty}, Legal);
> +
>   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL}) {
>     // These operations naturally get the right answer when used on
>     // GPR32, even if the actual type is narrower.
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll Fri Jun 30 13:27:36 2017
> @@ -158,15 +158,30 @@ define fp128 @test_quad_dump() {
> ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement)
> ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement
> ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement:
> + at var = global <2 x i16*> zeroinitializer
> define void @vector_of_pointers_extractelement() {
> -  %dummy = extractelement <2 x i16*> undef, i32 0
> +  br label %end
> +
> +block:
> +  %dummy = extractelement <2 x i16*> %vec, i32 0
>   ret void
> +
> +end:
> +  %vec = load <2 x i16*>, <2 x i16*>* undef
> +  br label %block
> }
> 
> ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(<2 x p0>) = G_INSERT_VECTOR_ELT %vreg1, %vreg2, %vreg3; (in function: vector_of_pointers_insertelement
> ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
> ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
> define void @vector_of_pointers_insertelement() {
> -  %dummy = insertelement <2 x i16*> undef, i16* null, i32 0
> +  br label %end
> +
> +block:
> +  %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
>   ret void
> +
> +end:
> +  %vec = load <2 x i16*>, <2 x i16*>* undef
> +  br label %block
> }
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Jun 30 13:27:36 2017
> @@ -577,7 +577,7 @@ define i32 @constant_int_start() {
> }
> 
> ; CHECK-LABEL: name: test_undef
> -; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
> +; CHECK: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
> ; CHECK: %w0 = COPY [[UNDEF]]
> define i32 @test_undef() {
>   ret i32 undef
> @@ -807,7 +807,7 @@ define float @test_frem(float %arg1, flo
> ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SADDO [[LHS]], [[RHS]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -824,7 +824,7 @@ define void @test_sadd_overflow(i32 %lhs
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -840,7 +840,7 @@ define void @test_uadd_overflow(i32 %lhs
> ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SSUBO [[LHS]], [[RHS]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -857,7 +857,7 @@ define void @test_ssub_overflow(i32 %lhs
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -873,7 +873,7 @@ define void @test_usub_overflow(i32 %lhs
> ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SMULO [[LHS]], [[RHS]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -889,7 +889,7 @@ define void @test_smul_overflow(i32 %lhs
> ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UMULO [[LHS]], [[RHS]]
> -; CHECK: [[TMP:%[0-9]+]](s64) = IMPLICIT_DEF
> +; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
> ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
> ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
> ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
> @@ -1503,7 +1503,7 @@ define float @test_different_call_conv_t
> define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
> ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
> ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
> ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
> @@ -1516,7 +1516,7 @@ define <2 x i32> @test_shufflevector_s32
> define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
> ; CHECK-LABEL: name: test_shufflevector_v2s32_s32
> ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
> ; CHECK: %w0 = COPY [[RES]](s32)
> @@ -1528,7 +1528,7 @@ define i32 @test_shufflevector_v2s32_s32
> define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
> ; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
> ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
> @@ -1541,7 +1541,7 @@ define <2 x i32> @test_shufflevector_v2s
> define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
> ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
> ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
> @@ -1570,7 +1570,7 @@ define <4 x i32> @test_shufflevector_v2s
> define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
> ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
> ; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
> ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
> @@ -1609,7 +1609,7 @@ define <16 x i8> @test_shufflevector_v8s
> }
> 
> ; CHECK-LABEL: test_constant_vector
> -; CHECK: [[UNDEF:%[0-9]+]](s16) = IMPLICIT_DEF
> +; CHECK: [[UNDEF:%[0-9]+]](s16) = G_IMPLICIT_DEF
> ; CHECK: [[F:%[0-9]+]](s16) = G_FCONSTANT half 0xH3C00
> ; CHECK: [[M:%[0-9]+]](<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
> ; CHECK: %d0 = COPY [[M]](<4 x s16>)
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll Fri Jun 30 13:27:36 2017
> @@ -64,7 +64,7 @@ define void @test_multiple_args(i64 %in)
> ; CHECK: [[I8:%[0-9]+]](s8) = COPY %w1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> 
> -; CHECK: [[UNDEF:%[0-9]+]](s192) = IMPLICIT_DEF
> +; CHECK: [[UNDEF:%[0-9]+]](s192) = G_IMPLICIT_DEF
> ; CHECK: [[ARG0:%[0-9]+]](s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
> ; CHECK: [[ARG1:%[0-9]+]](s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
> ; CHECK: [[ARG2:%[0-9]+]](s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll Fri Jun 30 13:27:36 2017
> @@ -19,7 +19,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
> 
> ; CHECK:   [[BAD]] (landing-pad):
> ; CHECK:     EH_LABEL
> -; CHECK:     [[UNDEF:%[0-9]+]](s128) = IMPLICIT_DEF
> +; CHECK:     [[UNDEF:%[0-9]+]](s128) = G_IMPLICIT_DEF
> ; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
> ; CHECK:     [[VAL_WITH_PTR:%[0-9]+]](s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
> ; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
> 
> Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir?rev=306875&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir (added)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir Fri Jun 30 13:27:36 2017
> @@ -0,0 +1,15 @@
> +# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
> +
> +---
> +name:            test_implicit_def
> +registers:
> +body: |
> +  bb.0.entry:
> +    liveins:
> +    ; CHECK-LABEL: name: test_implicit_def
> +    ; CHECK: [[LO:%[0-9]+]](s64) = G_IMPLICIT_DEF
> +    ; CHECK: [[HI:%[0-9]+]](s64) = G_IMPLICIT_DEF
> +    ; CHECK: %0(s128) = G_MERGE_VALUES [[LO]](s64), [[HI]](s64)
> +
> +    %0:_(s128) = G_IMPLICIT_DEF
> +...
> 
> Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll?rev=306875&r1=306874&r2=306875&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll Fri Jun 30 13:27:36 2017
> @@ -910,7 +910,7 @@ define arm_aapcscc {i32, i32} @test_stru
> define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
> ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
> ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
> ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
> @@ -925,7 +925,7 @@ define i32 @test_shufflevector_v2s32_v3s
> ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
> ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
> @@ -945,7 +945,7 @@ define i32 @test_shufflevector_v2s32_v4s
> ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
> ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32)
> @@ -966,7 +966,7 @@ define i32 @test_shufflevector_v4s32_v2s
> ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
> ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %r2
> ; CHECK: [[ARG4:%[0-9]+]](s32) = COPY %r3
> -; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
> +; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
> ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
> ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK-DAG: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
> @@ -1009,7 +1009,7 @@ define i32 @test_constantstruct_v2s32_s3
> ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
> ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
> ; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
> -; CHECK: [[C5:%[0-9]+]](s128) = IMPLICIT_DEF
> +; CHECK: [[C5:%[0-9]+]](s128) = G_IMPLICIT_DEF
> ; CHECK: [[C6:%[0-9]+]](s128) = G_INSERT [[C5]], [[VEC]](<2 x s32>), 0
> ; CHECK: [[C7:%[0-9]+]](s128) = G_INSERT [[C6]], [[C3]](s32), 64
> ; CHECK: [[C8:%[0-9]+]](s128) = G_INSERT [[C7]], [[C4]](s32), 96
> 
> 
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