[PATCH] D34757: [PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs created this revision.

On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris.
But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR).

This patch makes backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate.

e.g. (x | 0xFFFFFFFF) should be

  	ori 3, 3, 65535
  	oris 3, 3, 65535

but now LLVM generates

  	li 4, 0
  	oris 4, 4, 65535
  	ori 4, 4, 65535
  	or 3, 3, 4


https://reviews.llvm.org/D34757

Files:
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  test/CodeGen/PowerPC/ori_imm32.ll

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