[PATCH] D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL306550: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions (authored by alelab01).

Changed prior to commit:
  https://reviews.llvm.org/D34743?vs=104359&id=104422#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34743

Files:
  llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
  llvm/trunk/test/CodeGen/AArch64/cond-br-tuning.ll


Index: llvm/trunk/test/CodeGen/AArch64/cond-br-tuning.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/cond-br-tuning.ll
+++ llvm/trunk/test/CodeGen/AArch64/cond-br-tuning.ll
@@ -83,7 +83,7 @@
 
 ; CHECK-LABEL: test_add_tbz:
 ; CHECK: adds
-; CHECK: b.ge
+; CHECK: b.pl
 ; CHECK: ret
 define void @test_add_tbz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -99,7 +99,7 @@
 
 ; CHECK-LABEL: test_subs_tbz:
 ; CHECK: subs
-; CHECK: b.ge
+; CHECK: b.pl
 ; CHECK: ret
 define void @test_subs_tbz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -115,7 +115,7 @@
 
 ; CHECK-LABEL: test_add_tbnz
 ; CHECK: adds
-; CHECK: b.lt
+; CHECK: b.mi
 ; CHECK: ret
 define void @test_add_tbnz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -131,7 +131,7 @@
 
 ; CHECK-LABEL: test_subs_tbnz
 ; CHECK: subs
-; CHECK: b.lt
+; CHECK: b.mi
 ; CHECK: ret
 define void @test_subs_tbnz(i32 %a, i32 %b, i32* %ptr) {
 entry:
Index: llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
@@ -22,7 +22,7 @@
 ///    cbz w8, .LBB1_2 -> b.eq .LBB1_2
 ///
 /// 3) sub w8, w0, w1       -> subs w8, w0, w1   ; w8 has multiple uses.
-///    tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2
+///    tbz w8, #31, .LBB6_2 -> b.pl .LBB6_2
 ///
 //===----------------------------------------------------------------------===//
 
@@ -129,11 +129,11 @@
     break;
   case AArch64::TBZW:
   case AArch64::TBZX:
-    CC = AArch64CC::GE;
+    CC = AArch64CC::PL;
     break;
   case AArch64::TBNZW:
   case AArch64::TBNZX:
-    CC = AArch64CC::LT;
+    CC = AArch64CC::MI;
     break;
   }
   return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))


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