[PATCH] D34472: [DAG] Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset

[Vadzim Dambrouski via Phabricator via llvm-commits]

pftbest added inline comments.


================
Comment at: test/CodeGen/MSP430/Inst16mm.ll:68
+; CHECK-DAG:	mov.w	2(r1), 6(r1)
+; CHECK-DAG:	mov.w	0(r1), 4(r1)
 }
----------------
RKSimon wrote:
> If these are DAG checks would it better to replace the hard coded registers with regex?
I think this test checks that we do direct memory to memory transfer without loading into intermediate register. r1 is a stack pointer, so it's fixed and cannot change.

What can change is the order of this two movs. Is there some CHECK keyword that ignores the order of instructions?


https://reviews.llvm.org/D34472