[PATCH] D34737: [InstCombine] Remove 64-bit bit width restriction from m_ConstantInt(uint64_t*&)

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

I think we only need to make sure the value fits in 64-bits not that bit width is 64-bit.

This helps places that use this for shift amounts since the shift amount needs to be the same bitwidth as the LHS, but can't be larger than the bit width.


https://reviews.llvm.org/D34737

Files:
  include/llvm/IR/PatternMatch.h
  test/Transforms/InstCombine/icmp.ll


Index: test/Transforms/InstCombine/icmp.ll
===================================================================
--- test/Transforms/InstCombine/icmp.ll
+++ test/Transforms/InstCombine/icmp.ll
@@ -765,13 +765,9 @@
 ; TODO we have a 64-bit or less restriction in the handling for this pattern. We should remove that and do the same thing we do above.
 define i1 @test52b(i128 %x1) {
 ; CHECK-LABEL: @test52b(
-; CHECK-NEXT:    [[CONV:%.*]] = and i128 [[X1:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i128 [[CONV]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr i128 [[X1]], 16
-; CHECK-NEXT:    [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
-; CHECK-NEXT:    [[CMP15:%.*]] = icmp eq i8 [[TMP3]], 76
-; CHECK-NEXT:    [[A:%.*]] = and i1 [[CMP]], [[CMP15]]
-; CHECK-NEXT:    ret i1 [[A]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i128 [[X1:%.*]], 16711935
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i128 [[TMP1]], 4980863
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %conv = and i128 %x1, 255
   %cmp = icmp eq i128 %conv, 127
Index: include/llvm/IR/PatternMatch.h
===================================================================
--- include/llvm/IR/PatternMatch.h
+++ include/llvm/IR/PatternMatch.h
@@ -378,8 +378,7 @@
 
   template <typename ITy> bool match(ITy *V) {
     if (const auto *CV = dyn_cast<ConstantInt>(V))
-      if (CV->getBitWidth() <= 64) {
-        return false;
+      if (CV->getValue().ule(UINT64_MAX)) {
         VR = CV->getZExtValue();
         return true;
       }


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