[llvm] r306458 - [Hexagon] Use proper predicate register state when expanding PS_vselect
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 12:59:46 PDT 2017
Author: kparzysz
Date: Tue Jun 27 12:59:46 2017
New Revision: 306458
URL: http://llvm.org/viewvc/llvm-project?rev=306458&view=rev
Log:
[Hexagon] Use proper predicate register state when expanding PS_vselect
Added:
llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=306458&r1=306457&r2=306458&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Jun 27 12:59:46 2017
@@ -1253,10 +1253,16 @@ bool HexagonInstrInfo::expandPostRAPseud
LivePhysRegs LiveAtMI(HRI);
getLiveRegsAt(LiveAtMI, MI);
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
+ unsigned PReg = Op1.getReg();
+ assert(Op1.getSubReg() == 0);
+ unsigned PState = getRegState(Op1);
+
if (Op0.getReg() != Op2.getReg()) {
+ unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
+ : PState;
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
.add(Op0)
- .add(Op1)
+ .addReg(PReg, S)
.add(Op2);
if (IsDestLive)
T.addReg(Op0.getReg(), RegState::Implicit);
@@ -1265,7 +1271,7 @@ bool HexagonInstrInfo::expandPostRAPseud
if (Op0.getReg() != Op3.getReg()) {
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
.add(Op0)
- .add(Op1)
+ .addReg(PReg, PState)
.add(Op3);
if (IsDestLive)
T.addReg(Op0.getReg(), RegState::Implicit);
@@ -1282,12 +1288,18 @@ bool HexagonInstrInfo::expandPostRAPseud
LivePhysRegs LiveAtMI(HRI);
getLiveRegsAt(LiveAtMI, MI);
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
+ unsigned PReg = Op1.getReg();
+ assert(Op1.getSubReg() == 0);
+ unsigned PState = getRegState(Op1);
if (Op0.getReg() != Op2.getReg()) {
+ unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
+ : PState;
unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
.add(Op0)
+ .addReg(PReg, S)
.add(Op1)
.addReg(SrcHi)
.addReg(SrcLo);
@@ -1300,7 +1312,7 @@ bool HexagonInstrInfo::expandPostRAPseud
unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
.add(Op0)
- .add(Op1)
+ .addReg(PReg, PState)
.addReg(SrcHi)
.addReg(SrcLo);
if (IsDestLive)
Added: llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll?rev=306458&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll Tue Jun 27 12:59:46 2017
@@ -0,0 +1,53 @@
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
+;
+; Check that this does not crash.
+
+target triple = "hexagon"
+
+; CHECK-LABEL: danny:
+; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
+; CHECK-DAG: if (![[PREG]]) [[VREG]]
+define void @danny() local_unnamed_addr #0 {
+b0:
+ %v1 = icmp eq i32 0, undef
+ %v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> undef
+ %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v2, <16 x i32> zeroinitializer, i32 2)
+ %v4 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %v3)
+ %v5 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v4)
+ %v6 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %v5, i32 62)
+ %v7 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v6)
+ store <16 x i32> %v7, <16 x i32>* undef, align 64
+ unreachable
+}
+
+declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #2
+declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #2
+declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
+declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
+declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #2
+
+; CHECK-LABEL: sammy:
+; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
+; CHECK-DAG: if (![[PREG]]) [[VREG]]
+define void @sammy() local_unnamed_addr #1 {
+b0:
+ %v1 = icmp eq i32 0, undef
+ %v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> undef
+ %v3 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %v2, <32 x i32> zeroinitializer, i32 2)
+ %v4 = tail call <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3)
+ %v5 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v4)
+ %v6 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %v5, i32 62)
+ %v7 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v6)
+ store <32 x i32> %v7, <32 x i32>* undef, align 128
+ unreachable
+}
+
+declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #2
+declare <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #2
+declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2
+declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2
+declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #2 = { nounwind readnone }
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