[llvm] r306405 - [mips] Add instruction aliases for ds(r|l)l.
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 06:35:17 PDT 2017
Author: sdardis
Date: Tue Jun 27 06:35:17 2017
New Revision: 306405
URL: http://llvm.org/viewvc/llvm-project?rev=306405&view=rev
Log:
[mips] Add instruction aliases for ds(r|l)l.
Add the instruction aliases for ds(r|l)l for the two operand alias
of ds(r|l)lv and the aliases ds(r|l)l with the three register operands.
Modified:
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td Tue Jun 27 06:35:17 2017
@@ -548,3 +548,15 @@ def : MipsInstAlias<"dnegu $rt, $rs",
def : MipsInstAlias<"dnegu $rt",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsll $rd, $rt, $rs",
+ (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
+ GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsrl $rd, $rt, $rs",
+ (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
+ GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsrl $rd, $rt",
+ (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
+ GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsll $rd, $rt",
+ (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
+ GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Jun 27 06:35:17 2017
@@ -748,9 +748,6 @@ let AdditionalPredicates = [NotInMicroMi
defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>,
GPR_64;
}
-def : MipsInstAlias<"dsll $rd, $rt, $rs",
- (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
- ISA_MIPS3;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dneg $rt, $rs",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
@@ -793,9 +790,18 @@ def : MipsInstAlias<"dsra $rd, $rt, $rs"
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"dsll $rd, $rt, $rs",
+ (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
+ ISA_MIPS3;
def : MipsInstAlias<"dsrl $rd, $rt, $rs",
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
+ def : MipsInstAlias<"dsrl $rd, $rt",
+ (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
+ ISA_MIPS3;
+ def : MipsInstAlias<"dsll $rd, $rt",
+ (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
+ ISA_MIPS3;
// Two operand (implicit 0 selector) versions:
def : MipsInstAlias<"dmtc0 $rt, $rd",
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Tue Jun 27 06:35:17 2017
@@ -24,6 +24,10 @@ a:
dextm $9, $6, 3, 39 # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4]
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x10]
+ dsll $4, $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x10]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x50]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x50]
ldpc $2, 16 # CHECK: ldpc $2, 16 # encoding: [0x78,0x58,0x00,0x02]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Tue Jun 27 06:35:17 2017
@@ -83,6 +83,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -95,6 +97,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Tue Jun 27 06:35:17 2017
@@ -115,6 +115,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -127,6 +129,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Tue Jun 27 06:35:17 2017
@@ -115,6 +115,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -127,6 +129,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Tue Jun 27 06:35:17 2017
@@ -122,6 +122,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -134,6 +136,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Tue Jun 27 06:35:17 2017
@@ -131,6 +131,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -143,6 +145,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Tue Jun 27 06:35:17 2017
@@ -131,6 +131,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -143,6 +145,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Tue Jun 27 06:35:17 2017
@@ -131,6 +131,8 @@ a:
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
@@ -143,6 +145,8 @@ a:
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=306405&r1=306404&r2=306405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Tue Jun 27 06:35:17 2017
@@ -125,9 +125,13 @@ a:
dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9c]
dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
- dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e]
- dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e]
- dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f]
+ dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e]
+ dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e]
+ dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f]
+ dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
+ dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
+ dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
+ dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dvp $4 # CHECK: dvp $4 # encoding: [0x41,0x64,0x00,0x24]
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