[llvm] r306370 - [GlobalISel][X86] Add fp32/62 legalizer, regbank-select, selection tests for G_FADD, G_FSUB, G_FMUL, G_FDIV. NFC.
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 00:01:54 PDT 2017
Author: ibreger
Date: Tue Jun 27 00:01:54 2017
New Revision: 306370
URL: http://llvm.org/viewvc/llvm-project?rev=306370&view=rev
Log:
[GlobalISel][X86] Add fp32/62 legalizer, regbank-select, selection tests for G_FADD, G_FSUB, G_FMUL, G_FDIV. NFC.
Added:
llvm/trunk/test/CodeGen/X86/GlobalISel/fadd-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/fdiv-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/fmul-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/fsub-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
Modified:
llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-add.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/fadd-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/fadd-scalar.ll?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/fadd-scalar.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/fadd-scalar.ll Tue Jun 27 00:01:54 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
+define float @test_fadd_float(float %arg1, float %arg2) {
+; ALL-LABEL: test_fadd_float:
+; ALL: # BB#0:
+; ALL-NEXT: addss %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fadd float %arg1, %arg2
+ ret float %ret
+}
+
+define double @test_fadd_double(double %arg1, double %arg2) {
+; ALL-LABEL: test_fadd_double:
+; ALL: # BB#0:
+; ALL-NEXT: addsd %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fadd double %arg1, %arg2
+ ret double %ret
+}
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/fdiv-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/fdiv-scalar.ll?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/fdiv-scalar.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/fdiv-scalar.ll Tue Jun 27 00:01:54 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
+define float @test_fdiv_float(float %arg1, float %arg2) {
+; ALL-LABEL: test_fdiv_float:
+; ALL: # BB#0:
+; ALL-NEXT: divss %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fdiv float %arg1, %arg2
+ ret float %ret
+}
+
+define double @test_fdiv_double(double %arg1, double %arg2) {
+; ALL-LABEL: test_fdiv_double:
+; ALL: # BB#0:
+; ALL-NEXT: divsd %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fdiv double %arg1, %arg2
+ ret double %ret
+}
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/fmul-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/fmul-scalar.ll?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/fmul-scalar.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/fmul-scalar.ll Tue Jun 27 00:01:54 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
+define float @test_fmul_float(float %arg1, float %arg2) {
+; ALL-LABEL: test_fmul_float:
+; ALL: # BB#0:
+; ALL-NEXT: mulss %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fmul float %arg1, %arg2
+ ret float %ret
+}
+
+define double @test_fmul_double(double %arg1, double %arg2) {
+; ALL-LABEL: test_fmul_double:
+; ALL: # BB#0:
+; ALL-NEXT: mulsd %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fmul double %arg1, %arg2
+ ret double %ret
+}
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/fsub-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/fsub-scalar.ll?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/fsub-scalar.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/fsub-scalar.ll Tue Jun 27 00:01:54 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
+define float @test_fsub_float(float %arg1, float %arg2) {
+; ALL-LABEL: test_fsub_float:
+; ALL: # BB#0:
+; ALL-NEXT: subss %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fsub float %arg1, %arg2
+ ret float %ret
+}
+
+define double @test_fsub_double(double %arg1, double %arg2) {
+; ALL-LABEL: test_fsub_double:
+; ALL: # BB#0:
+; ALL-NEXT: subsd %xmm1, %xmm0
+; ALL-NEXT: retq
+ %ret = fsub double %arg1, %arg2
+ ret double %ret
+}
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,74 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+
+ define float @test_fadd_float(float %arg1, float %arg2) {
+ %ret = fadd float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fadd_double(double %arg1, double %arg2) {
+ %ret = fadd double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fadd_float
+# CHECK-LABEL: name: test_fadd_float
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s32) = COPY %xmm0
+# CHECK-NEXT: %1(s32) = COPY %xmm1
+# CHECK-NEXT: %2(s32) = G_FADD %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s32)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FADD %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fadd_double
+# CHECK-LABEL: name: test_fadd_double
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s64) = COPY %xmm0
+# CHECK-NEXT: %1(s64) = COPY %xmm1
+# CHECK-NEXT: %2(s64) = G_FADD %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s64)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FADD %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,74 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+
+ define float @test_fdiv_float(float %arg1, float %arg2) {
+ %ret = fdiv float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fdiv_double(double %arg1, double %arg2) {
+ %ret = fdiv double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fdiv_float
+# CHECK-LABEL: name: test_fdiv_float
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s32) = COPY %xmm0
+# CHECK-NEXT: %1(s32) = COPY %xmm1
+# CHECK-NEXT: %2(s32) = G_FDIV %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s32)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fdiv_double
+# CHECK-LABEL: name: test_fdiv_double
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s64) = COPY %xmm0
+# CHECK-NEXT: %1(s64) = COPY %xmm1
+# CHECK-NEXT: %2(s64) = G_FDIV %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s64)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,74 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+
+ define float @test_fmul_float(float %arg1, float %arg2) {
+ %ret = fmul float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fmul_double(double %arg1, double %arg2) {
+ %ret = fmul double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fmul_float
+# CHECK-LABEL: name: test_fmul_float
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s32) = COPY %xmm0
+# CHECK-NEXT: %1(s32) = COPY %xmm1
+# CHECK-NEXT: %2(s32) = G_FMUL %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s32)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FMUL %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fmul_double
+# CHECK-LABEL: name: test_fmul_double
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s64) = COPY %xmm0
+# CHECK-NEXT: %1(s64) = COPY %xmm1
+# CHECK-NEXT: %2(s64) = G_FMUL %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s64)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FMUL %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,74 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+
+ define float @test_fsub_float(float %arg1, float %arg2) {
+ %ret = fsub float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fsub_double(double %arg1, double %arg2) {
+ %ret = fsub double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fsub_float
+# CHECK-LABEL: name: test_fsub_float
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s32) = COPY %xmm0
+# CHECK-NEXT: %1(s32) = COPY %xmm1
+# CHECK-NEXT: %2(s32) = G_FSUB %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s32)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FSUB %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fsub_double
+# CHECK-LABEL: name: test_fsub_double
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# CHECK: %0(s64) = COPY %xmm0
+# CHECK-NEXT: %1(s64) = COPY %xmm1
+# CHECK-NEXT: %2(s64) = G_FSUB %0, %1
+# CHECK-NEXT: %xmm0 = COPY %2(s64)
+# CHECK-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FSUB %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir?rev=306370&r1=306369&r2=306370&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir Tue Jun 27 00:01:54 2017
@@ -35,6 +35,25 @@
%ret = fadd double %arg1, %arg2
ret double %ret
}
+
+ define void @test_fsub_float() {
+ %ret1 = fsub float undef, undef
+ %ret2 = fsub double undef, undef
+ ret void
+ }
+
+ define void @test_fmul_float() {
+ %ret1 = fmul float undef, undef
+ %ret2 = fmul double undef, undef
+ ret void
+ }
+
+ define void @test_fdiv_float() {
+ %ret1 = fdiv float undef, undef
+ %ret2 = fdiv double undef, undef
+ ret void
+ }
+
define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = add <4 x i32> %arg1, %arg2
@@ -338,6 +357,105 @@ body: |
...
---
+name: test_fsub_float
+# CHECK-LABEL: name: test_fsub_float
+alignment: 4
+legalized: true
+regBankSelected: false
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ %0(s32) = IMPLICIT_DEF
+ %2(s64) = IMPLICIT_DEF
+ %1(s32) = G_FSUB %0, %0
+ %3(s64) = G_FSUB %2, %2
+ RET 0
+
+...
+---
+name: test_fmul_float
+# CHECK-LABEL: name: test_fmul_float
+alignment: 4
+legalized: true
+regBankSelected: false
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ %0(s32) = IMPLICIT_DEF
+ %2(s64) = IMPLICIT_DEF
+ %1(s32) = G_FMUL %0, %0
+ %3(s64) = G_FMUL %2, %2
+ RET 0
+
+...
+---
+name: test_fdiv_float
+# CHECK-LABEL: name: test_fdiv_float
+alignment: 4
+legalized: true
+regBankSelected: false
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ %0(s32) = IMPLICIT_DEF
+ %2(s64) = IMPLICIT_DEF
+ %1(s32) = G_FDIV %0, %0
+ %3(s64) = G_FDIV %2, %2
+ RET 0
+
+...
+---
name: test_add_v4i32
alignment: 4
legalized: true
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-add.mir?rev=306370&r1=306369&r2=306370&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-add.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-add.mir Tue Jun 27 00:01:54 2017
@@ -24,16 +24,6 @@
ret i8 %ret
}
- define float @test_add_float(float %arg1, float %arg2) {
- %ret = fadd float %arg1, %arg2
- ret float %ret
- }
-
- define double @test_add_double(double %arg1, double %arg2) {
- %ret = fadd double %arg1, %arg2
- ret double %ret
- }
-
define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = add <4 x i32> %arg1, %arg2
ret <4 x i32> %ret
@@ -157,76 +147,6 @@ body: |
...
---
-name: test_add_float
-# ALL-LABEL: name: test_add_float
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
-registers:
- - { id: 0, class: vecr }
- - { id: 1, class: vecr }
- - { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = ADDSSrr %0, %1
-# AVX-NEXT: %2 = VADDSSrr %0, %1
-# AVX512F-NEXT: %2 = VADDSSZrr %0, %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %xmm0, %xmm1
-
- %0(s32) = COPY %xmm0
- %1(s32) = COPY %xmm1
- %2(s32) = G_FADD %0, %1
- %xmm0 = COPY %2(s32)
- RET 0, implicit %xmm0
-
-...
----
-name: test_add_double
-# ALL-LABEL: name: test_add_double
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
-registers:
- - { id: 0, class: vecr }
- - { id: 1, class: vecr }
- - { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = ADDSDrr %0, %1
-# AVX-NEXT: %2 = VADDSDrr %0, %1
-# AVX512F-NEXT: %2 = VADDSDZrr %0, %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %xmm0, %xmm1
-
- %0(s64) = COPY %xmm0
- %1(s64) = COPY %xmm1
- %2(s64) = G_FADD %0, %1
- %xmm0 = COPY %2(s64)
- RET 0, implicit %xmm0
-
-...
----
name: test_add_v4i32
# ALL-LABEL: name: test_add_v4i32
alignment: 4
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,119 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+--- |
+
+ define float @test_fadd_float(float %arg1, float %arg2) {
+ %ret = fadd float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fadd_double(double %arg1, double %arg2) {
+ %ret = fadd double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fadd_float
+# ALL-LABEL: name: test_fadd_float
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = ADDSSrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VADDSSrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VADDSSZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FADD %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fadd_double
+# ALL-LABEL: name: test_fadd_double
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = ADDSDrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VADDSDrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VADDSDZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FADD %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,119 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+--- |
+
+ define float @test_fdiv_float(float %arg1, float %arg2) {
+ %ret = fdiv float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fdiv_double(double %arg1, double %arg2) {
+ %ret = fdiv double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fdiv_float
+# ALL-LABEL: name: test_fdiv_float
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = DIVSSrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VDIVSSrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VDIVSSZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fdiv_double
+# ALL-LABEL: name: test_fdiv_double
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = DIVSDrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VDIVSDrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VDIVSDZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,119 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+--- |
+
+ define float @test_fmul_float(float %arg1, float %arg2) {
+ %ret = fmul float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fmul_double(double %arg1, double %arg2) {
+ %ret = fmul double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fmul_float
+# ALL-LABEL: name: test_fmul_float
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = MULSSrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VMULSSrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VMULSSZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FMUL %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fmul_double
+# ALL-LABEL: name: test_fmul_double
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = MULSDrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VMULSDrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VMULSDZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FMUL %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir?rev=306370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir Tue Jun 27 00:01:54 2017
@@ -0,0 +1,119 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+--- |
+
+ define float @test_fsub_float(float %arg1, float %arg2) {
+ %ret = fsub float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fsub_double(double %arg1, double %arg2) {
+ %ret = fsub double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fsub_float
+# ALL-LABEL: name: test_fsub_float
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = SUBSSrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VSUBSSrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VSUBSSZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FSUB %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fsub_double
+# ALL-LABEL: name: test_fsub_double
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = SUBSDrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VSUBSDrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VSUBSDZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FSUB %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir?rev=306370&r1=306369&r2=306370&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir Tue Jun 27 00:01:54 2017
@@ -14,16 +14,6 @@
ret i32 %ret
}
- define float @test_sub_float(float %arg1, float %arg2) {
- %ret = fsub float %arg1, %arg2
- ret float %ret
- }
-
- define double @test_sub_double(double %arg1, double %arg2) {
- %ret = fsub double %arg1, %arg2
- ret double %ret
- }
-
define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = sub <4 x i32> %arg1, %arg2
ret <4 x i32> %ret
@@ -87,73 +77,6 @@ body: |
...
---
-name: test_sub_float
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
-registers:
- - { id: 0, class: vecr }
- - { id: 1, class: vecr }
- - { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = SUBSSrr %0, %1
-# AVX-NEXT: %2 = VSUBSSrr %0, %1
-# AVX512F-NEXT: %2 = VSUBSSZrr %0, %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %xmm0, %xmm1
-
- %0(s32) = COPY %xmm0
- %1(s32) = COPY %xmm1
- %2(s32) = G_FSUB %0, %1
- %xmm0 = COPY %2(s32)
- RET 0, implicit %xmm0
-
-...
----
-name: test_sub_double
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
-registers:
- - { id: 0, class: vecr }
- - { id: 1, class: vecr }
- - { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = SUBSDrr %0, %1
-# AVX-NEXT: %2 = VSUBSDrr %0, %1
-# AVX512F-NEXT: %2 = VSUBSDZrr %0, %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %xmm0, %xmm1
-
- %0(s64) = COPY %xmm0
- %1(s64) = COPY %xmm1
- %2(s64) = G_FSUB %0, %1
- %xmm0 = COPY %2(s64)
- RET 0, implicit %xmm0
-...
----
name: test_sub_v4i32
alignment: 4
legalized: true
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