[PATCH] D34503: AVX-512: Fixed a crash during legalization of <3 x i8> type

[Elena Demikhovsky via Phabricator via llvm-commits]

delena updated this revision to Diff 103864.
delena added a comment.

Code changes according to Simon's comments.


Repository:
  rL LLVM

https://reviews.llvm.org/D34503

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  test/CodeGen/X86/avx512-vec3-crash.ll


Index: test/CodeGen/X86/avx512-vec3-crash.ll
===================================================================
--- test/CodeGen/X86/avx512-vec3-crash.ll
+++ test/CodeGen/X86/avx512-vec3-crash.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=skx -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; This test crashed during type legalization of SETCC result type.
+define <3 x i8 > @foo(<3 x i8>%x, <3 x i8>%a, <3 x i8>%b) {
+; CHECK-LABEL: foo:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovd %edi, %xmm0
+; CHECK-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrd $2, %edx, %xmm0, %xmm0
+; CHECK-NEXT:    vpslld $24, %xmm0, %xmm0
+; CHECK-NEXT:    vpsrad $24, %xmm0, %xmm0
+; CHECK-NEXT:    vmovd %ecx, %xmm1
+; CHECK-NEXT:    vpinsrd $1, %r8d, %xmm1, %xmm1
+; CHECK-NEXT:    vpinsrd $2, %r9d, %xmm1, %xmm1
+; CHECK-NEXT:    vpslld $24, %xmm1, %xmm1
+; CHECK-NEXT:    vpsrad $24, %xmm1, %xmm1
+; CHECK-NEXT:    vpcmpgtd %xmm0, %xmm1, %k0
+; CHECK-NEXT:    vpmovm2d %k0, %xmm0
+; CHECK-NEXT:    vpextrb $0, %xmm0, %eax
+; CHECK-NEXT:    vpextrb $4, %xmm0, %edx
+; CHECK-NEXT:    vpextrb $8, %xmm0, %ecx
+; CHECK-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT:    # kill: %DL<def> %DL<kill> %EDX<kill>
+; CHECK-NEXT:    # kill: %CL<def> %CL<kill> %ECX<kill>
+; CHECK-NEXT:    retq
+  %cmp.i = icmp slt <3 x i8> %x, %a
+  %res = sext <3 x i1> %cmp.i to <3 x i8>
+  ret <3 x i8> %res
+}
+
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -615,9 +615,8 @@
   SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
                               N->getOperand(2));
 
-  assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
   // Convert to the expected type.
-  return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
+  return DAG.getSExtOrTrunc(SetCC, dl, NVT);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {


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