[llvm] r306211 - fix trivial typos in comment, NFC

[Hiroshi Inoue via llvm-commits]

Author: inouehrs
Date: Sat Jun 24 11:00:26 2017
New Revision: 306211

URL: http://llvm.org/viewvc/llvm-project?rev=306211&view=rev
Log:
fix trivial typos in comment, NFC


Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
    llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
    llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=306211&r1=306210&r2=306211&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Sat Jun 24 11:00:26 2017
@@ -58,7 +58,7 @@
 //
 // The struct type node has a name and a list of pairs, one pair for each member
 // of the struct. The first element of each pair is a type node (a struct type
-// node or a sclar type node), specifying the type of the member, the second
+// node or a scalar type node), specifying the type of the member, the second
 // element of each pair is the offset of the member.
 //
 // Given an example

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td?rev=306211&r1=306210&r2=306211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td Sat Jun 24 11:00:26 2017
@@ -13,7 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// The Cortex-A57 is a traditional superscaler microprocessor with a
+// The Cortex-A57 is a traditional superscalar microprocessor with a
 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
 // much wider out-of-order issue stage, this produced a need to carefully
 // schedule micro-ops so that all three decoded each cycle are successfully

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll?rev=306211&r1=306210&r2=306211&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll Sat Jun 24 11:00:26 2017
@@ -3,7 +3,7 @@
 ; The DAGCombiner tries to do following shrink:
 ;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
 ; But currently it can't handle vector type and will trigger an assertion failure
-; when it tries to generate an add mixed using vector type and scaler type.
+; when it tries to generate an add mixed using vector type and scalar type.
 ; This test checks that such assertion failur should not happen.
 define <1 x i64> @dotest(<1 x i64> %in0) {
 entry: