[llvm] r306117 - [SystemZ] Remove unnecessary serialization before volatile loads
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 23 08:56:16 PDT 2017
Author: uweigand
Date: Fri Jun 23 10:56:14 2017
New Revision: 306117
URL: http://llvm.org/viewvc/llvm-project?rev=306117&view=rev
Log:
[SystemZ] Remove unnecessary serialization before volatile loads
This reverts the use of TargetLowering::prepareVolatileOrAtomicLoad
introduced by r196905. Nothing in the semantics of the "volatile"
keyword or the definition of the z/Architecture actually requires
that volatile loads are preceded by a serialization operation, and
no other compiler on the platform actually implements this.
Since we've now seen a use case where this additional serialization
causes noticable performance degradation, this patch removes it.
The patch still leaves in the serialization before atomic loads,
which is now implemented directly in lowerATOMIC_LOAD. (This also
seems overkill, but that can be addressed separately.)
Removed:
llvm/trunk/test/CodeGen/SystemZ/serialize-01.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=306117&r1=306116&r2=306117&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Fri Jun 23 10:56:14 2017
@@ -1322,11 +1322,6 @@ SystemZTargetLowering::LowerReturn(SDVal
return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
}
-SDValue SystemZTargetLowering::prepareVolatileOrAtomicLoad(
- SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const {
- return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
-}
-
// Return true if Op is an intrinsic node with chain that returns the CC value
// as its only (other) argument. Provide the associated SystemZISD opcode and
// the mask of valid CC values if so.
@@ -3212,12 +3207,15 @@ SDValue SystemZTargetLowering::lowerATOM
return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
}
-// Op is an atomic load. Lower it into a normal volatile load.
+// Op is an atomic load. Lower it into a serialization followed
+// by a normal volatile load.
SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
SelectionDAG &DAG) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());
+ SDValue Chain = SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op),
+ MVT::Other, Node->getChain()), 0);
return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
- Node->getChain(), Node->getBasePtr(),
+ Chain, Node->getBasePtr(),
Node->getMemoryVT(), Node->getMemOperand());
}
@@ -4688,7 +4686,6 @@ const char *SystemZTargetLowering::getTa
OPCODE(STRCMP);
OPCODE(SEARCH_STRING);
OPCODE(IPM);
- OPCODE(SERIALIZE);
OPCODE(MEMBARRIER);
OPCODE(TBEGIN);
OPCODE(TBEGIN_NOFLOAT);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=306117&r1=306116&r2=306117&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Fri Jun 23 10:56:14 2017
@@ -139,9 +139,6 @@ enum NodeType : unsigned {
// Store the CC value in bits 29 and 28 of an integer.
IPM,
- // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
- SERIALIZE,
-
// Compiler barrier only; generate a no-op.
MEMBARRIER,
@@ -471,8 +468,6 @@ public:
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
SelectionDAG &DAG) const override;
- SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
- SelectionDAG &DAG) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
ISD::NodeType getExtendForAtomicOps() const override {
@@ -522,7 +517,6 @@ private:
unsigned Opcode) const;
SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=306117&r1=306116&r2=306117&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Fri Jun 23 10:56:14 2017
@@ -1446,7 +1446,7 @@ let Predicates = [FeatureExecutionHint]
// A serialization instruction that acts as a barrier for all memory
// accesses, which expands to "bcr 14, 0".
let hasSideEffects = 1 in
-def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
+def Serialize : Alias<2, (outs), (ins), []>;
// A pseudo instruction that serves as a compiler barrier.
let hasSideEffects = 1, hasNoSchedulingInfo = 1 in
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperators.td?rev=306117&r1=306116&r2=306117&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td Fri Jun 23 10:56:14 2017
@@ -191,8 +191,6 @@ def z_sdivrem64 : SDNode<"System
def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
-def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
- [SDNPHasChain, SDNPMayStore]>;
def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
Removed: llvm/trunk/test/CodeGen/SystemZ/serialize-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/serialize-01.ll?rev=306116&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/serialize-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/serialize-01.ll (removed)
@@ -1,21 +0,0 @@
-; Test serialization instructions.
-;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
-; RUN: FileCheck %s -check-prefix=CHECK-FULL
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | \
-; RUN: FileCheck %s -check-prefix=CHECK-FAST
-
-; Check that volatile loads produce a serialisation.
-define i32 @f1(i32 *%src) {
-; CHECK-FULL-LABEL: f1:
-; CHECK-FULL: bcr 15, %r0
-; CHECK-FULL: l %r2, 0(%r2)
-; CHECK-FULL: br %r14
-;
-; CHECK-FAST-LABEL: f1:
-; CHECK-FAST: bcr 14, %r0
-; CHECK-FAST: l %r2, 0(%r2)
-; CHECK-FAST: br %r14
- %val = load volatile i32 , i32 *%src
- ret i32 %val
-}
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