[PATCH] D34391: [RegisterCoalescer] Fix for SubRange join unreachable

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 21 13:55:16 PDT 2017


arsenm added a comment.

In https://reviews.llvm.org/D34391#786456, @dstuttard wrote:

> Updating the test as per review comments
>
> I've left it as a .ll test rather than .mir as the mir print routines can't cope
>  with pseudo source values (used in the llvm.amdgcn.buffer.load intrinsics)
>
> "TargetCustom pseudo source values are not supported"


You can strip out the MemOperands in the MIR test



================
Comment at: test/CodeGen/AMDGPU/pr33524.ll:1
+; ModuleID = 'pr33524.bc'
+source_filename = "bugpoint-output-3331cb1.bc"
----------------
qcolombet wrote:
> You need to add a RUN line and some FileCheck command to check we are generating correct code.
> FWIW, you'll have something more robust with a .mir test (llc -stop-before simple-register-coalescing -simplify-mir)
> Add a comment on what this test is checking. In particular listing the pr number here is a good practice.
> Give a meaning full name to the filename, e.g., reg-coal-join-subrange.
Remove these extra comments


================
Comment at: test/CodeGen/AMDGPU/pr33524.ll:2-4
+source_filename = "bugpoint-output-3331cb1.bc"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024"
+target triple = "spir64-unknown-unknown"
----------------
These will be redundant with the run line


================
Comment at: test/CodeGen/AMDGPU/pr33524.ll:67-70
+!spirv.Generator = !{!0}
+
+!0 = !{i16 8, i16 1}
+!1 = !{}
----------------
You can remove all the metadata


https://reviews.llvm.org/D34391





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