[PATCH] D34032: [Power9] Exploit vector extract with variable index

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added inline comments.


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Comment at: test/CodeGen/PowerPC/vec_extract_p9.ll:117
+; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE-NEXT:    li 3, 1
+; CHECK-LE-NEXT:    vextubrx 3, 3, 2
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This is probably fine. I have more of a question here...
I see that throughout the tests (not just here) the registers used are specified. 
While the register allocator is most likely to pick r3 in this case is that a guarantee? The load immediate is not constrained by the ABI so technically it could use a different register and this is still correct. 


https://reviews.llvm.org/D34032