[PATCH] D34402: [AArch64] Preserve register flags when promoting a load from store.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

This ppatch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved. As a load can only be promoted from a load, if the operand is
not modified between the store and load instructions, the flags of the
operand should always be the same, I think.

This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).


https://reviews.llvm.org/D34402

Files:
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  test/CodeGen/AArch64/ldst-opt.mir


Index: test/CodeGen/AArch64/ldst-opt.mir
===================================================================
--- test/CodeGen/AArch64/ldst-opt.mir
+++ test/CodeGen/AArch64/ldst-opt.mir
@@ -34,7 +34,7 @@
 # Don't count transient instructions towards search limits.
 # CHECK-LABEL: name: promote-load-from-store
 # CHECK: STRWui %w1
-# CHECK: UBFMWri %w1
+# CHECK: UBFMWri killed %w1
 ---
 name: store-pair
 tracksRegLiveness: true
@@ -144,3 +144,22 @@
 # CHECK: %wzr = COPY %w1
 # CHECK: %w11 = ORRWrs %wzr, %w1, 0
 # CHECK: HINT 0, implicit %w11
+---
+name: promote-load-from-store-undef
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %w1, %x0, %x2, %lr
+
+    STRWui undef %w1, %x0, 0 :: (store 4)
+    %w0 = LDRBBui %x0, 1 :: (load 2)
+    STRHHui undef %w3, %x2, 0 :: (store 4)
+    %w1 = LDRBBui %x2, 0 :: (load 4)
+    RET %lr, implicit %w0
+
+...
+# CHECK-LABEL: name: promote-load-from-store-undef
+# CHECK: STRWui undef %w1
+# CHECK: UBFMWri undef %w1
+# CHECK: STRHHui undef %w3
+# CHECK: ANDWri undef %w3
Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -795,6 +795,7 @@
   int LoadSize = getMemScale(*LoadI);
   int StoreSize = getMemScale(*StoreI);
   unsigned LdRt = getLdStRegOp(*LoadI).getReg();
+  const MachineOperand &StMO = getLdStRegOp(*StoreI);
   unsigned StRt = getLdStRegOp(*StoreI).getReg();
   bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
 
@@ -819,7 +820,7 @@
         BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
             .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
-            .addReg(StRt)
+            .add(StMO)
             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
   } else {
     // FIXME: Currently we disable this transformation in big-endian targets as
@@ -860,14 +861,14 @@
           BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                   TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
                   DestReg)
-              .addReg(StRt)
+              .add(StMO)
               .addImm(AndMaskEncoded);
     } else {
       BitExtMI =
           BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                   TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
                   DestReg)
-              .addReg(StRt)
+              .add(StMO)
               .addImm(Immr)
               .addImm(Imms);
     }


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