[PATCH] D34396: Adding code padding for performance stability - first policy (BranchesWithSameTargetAvoidancePolicy)

[Omer Paparo Bivas via Phabricator via llvm-commits]

opaparo created this revision.
Herald added a subscriber: mgorny.

This patch relies on an infrastructure introduced in a previous patch <https://reviews.llvm.org/D34393>.

In the Intel Architectures Optimization Reference Manual <https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf>, under the clause "Branch Prediction Optimization", the following optimization is suggested: "Avoid putting two conditional branch instructions in a loop so that both have the same branch target address and, at the same time, belong to (i.e.have their last bytes' addresses within) the same 16-byte aligned code block.".

In this patch a new policy is introduced. This new policy implements the above suggestion by inserting MCPaddingFragments before hazardous instructions (i.e. jmps whose target address is computable at compilation time) and returning positive penalty weight for 16 Byte windows that contain the said situation.


Repository:
  rL LLVM

https://reviews.llvm.org/D34396

Files:
  lib/Target/X86/MCTargetDesc/CMakeLists.txt
  lib/Target/X86/MCTargetDesc/LLVMBuild.txt
  lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  lib/Target/X86/MCTargetDesc/X86MCCodePadder.cpp
  lib/Target/X86/MCTargetDesc/X86MCCodePadder.h
  lib\Target\X86\MCTargetDesc\X86MCCodePadder.cpp
  lib\Target\X86\MCTargetDesc\X86MCCodePadder.h
  test/CodeGen/X86/perf_nops.mir

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