[llvm] r305752 - [AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands (e.g. blockaddress).
Geoff Berry via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 19 14:57:44 PDT 2017
Author: gberry
Date: Mon Jun 19 16:57:44 2017
New Revision: 305752
URL: http://llvm.org/viewvc/llvm-project?rev=305752&view=rev
Log:
[AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands (e.g. blockaddress).
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td?rev=305752&r1=305751&r2=305752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td Mon Jun 19 16:57:44 2017
@@ -519,7 +519,8 @@ def FalkorReadIncSt : SchedReadAdvance<
// SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast
// -----------------------------------------------------------------------------
-def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>;
+def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0}]>;
def FalkorOp1ZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR ||
MI->getOperand(1).getReg() == AArch64::XZR}]>;
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