[llvm] r305656 - [x86] specify triples and auto-generate complete checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 18 14:48:44 PDT 2017
Author: spatel
Date: Sun Jun 18 16:48:44 2017
New Revision: 305656
URL: http://llvm.org/viewvc/llvm-project?rev=305656&view=rev
Log:
[x86] specify triples and auto-generate complete checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/widen_arith-4.ll
llvm/trunk/test/CodeGen/X86/widen_arith-5.ll
llvm/trunk/test/CodeGen/X86/widen_arith-6.ll
Modified: llvm/trunk/test/CodeGen/X86/widen_arith-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-4.ll?rev=305656&r1=305655&r2=305656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_arith-4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_arith-4.ll Sun Jun 18 16:48:44 2017
@@ -1,16 +1,47 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
-; CHECK: psubw
-; CHECK-NEXT: pmullw
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
; Widen a v5i16 to v8i16 to do a vector sub and multiple
define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
+; CHECK-LABEL: update:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movw $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u>
+; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <2,4,2,2,2,u,u,u>
+; CHECK-NEXT: jmp .LBB0_1
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_2: # %forbody
+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: shlq $4, %rcx
+; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: movdqa (%rdx,%rcx), %xmm2
+; CHECK-NEXT: psubw %xmm0, %xmm2
+; CHECK-NEXT: pmullw %xmm1, %xmm2
+; CHECK-NEXT: pextrw $4, %xmm2, 8(%rax,%rcx)
+; CHECK-NEXT: movq %xmm2, (%rax,%rcx)
+; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: .LBB0_1: # %forcond
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: jl .LBB0_2
+; CHECK-NEXT: # BB#3: # %afterfor
+; CHECK-NEXT: retq
entry:
- %dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
- %src.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
- %n.addr = alloca i32 ; <i32*> [#uses=2]
- %v = alloca <5 x i16>, align 16 ; <<5 x i16>*> [#uses=1]
- %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ %dst.addr = alloca <5 x i16>*
+ %src.addr = alloca <5 x i16>*
+ %n.addr = alloca i32
+ %v = alloca <5 x i16>, align 16
+ %i = alloca i32, align 4
store <5 x i16>* %dst, <5 x i16>** %dst.addr
store <5 x i16>* %src, <5 x i16>** %src.addr
store i32 %n, i32* %n.addr
@@ -18,32 +49,32 @@ entry:
store i32 0, i32* %i
br label %forcond
-forcond: ; preds = %forinc, %entry
- %tmp = load i32, i32* %i ; <i32> [#uses=1]
- %tmp1 = load i32, i32* %n.addr ; <i32> [#uses=1]
- %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+forcond:
+ %tmp = load i32, i32* %i
+ %tmp1 = load i32, i32* %n.addr
+ %cmp = icmp slt i32 %tmp, %tmp1
br i1 %cmp, label %forbody, label %afterfor
-forbody: ; preds = %forcond
- %tmp2 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp3 = load <5 x i16>*, <5 x i16>** %dst.addr ; <<5 x i16>*> [#uses=1]
- %arrayidx = getelementptr <5 x i16>, <5 x i16>* %tmp3, i32 %tmp2 ; <<5 x i16>*> [#uses=1]
- %tmp4 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp5 = load <5 x i16>*, <5 x i16>** %src.addr ; <<5 x i16>*> [#uses=1]
- %arrayidx6 = getelementptr <5 x i16>, <5 x i16>* %tmp5, i32 %tmp4 ; <<5 x i16>*> [#uses=1]
- %tmp7 = load <5 x i16>, <5 x i16>* %arrayidx6 ; <<5 x i16>> [#uses=1]
- %sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 > ; <<5 x i16>> [#uses=1]
- %mul = mul <5 x i16> %sub, < i16 2, i16 4, i16 2, i16 2, i16 2 > ; <<5 x i16>> [#uses=1]
+forbody:
+ %tmp2 = load i32, i32* %i
+ %tmp3 = load <5 x i16>*, <5 x i16>** %dst.addr
+ %arrayidx = getelementptr <5 x i16>, <5 x i16>* %tmp3, i32 %tmp2
+ %tmp4 = load i32, i32* %i
+ %tmp5 = load <5 x i16>*, <5 x i16>** %src.addr
+ %arrayidx6 = getelementptr <5 x i16>, <5 x i16>* %tmp5, i32 %tmp4
+ %tmp7 = load <5 x i16>, <5 x i16>* %arrayidx6
+ %sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 >
+ %mul = mul <5 x i16> %sub, < i16 2, i16 4, i16 2, i16 2, i16 2 >
store <5 x i16> %mul, <5 x i16>* %arrayidx
br label %forinc
-forinc: ; preds = %forbody
- %tmp8 = load i32, i32* %i ; <i32> [#uses=1]
- %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+forinc:
+ %tmp8 = load i32, i32* %i
+ %inc = add i32 %tmp8, 1
store i32 %inc, i32* %i
br label %forcond
-afterfor: ; preds = %forcond
+afterfor:
ret void
}
Modified: llvm/trunk/test/CodeGen/X86/widen_arith-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-5.ll?rev=305656&r1=305655&r2=305656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_arith-5.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_arith-5.ll Sun Jun 18 16:48:44 2017
@@ -1,17 +1,46 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
-; CHECK: movdqa
-; CHECK: pslld $2
-; CHECK: psubd
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
; widen a v3i32 to v4i32 to do a vector multiple and a subtraction
define void @update(<3 x i32>* %dst, <3 x i32>* %src, i32 %n) nounwind {
+; CHECK-LABEL: update:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq {{.*}}(%rip), %rax
+; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <3,3,3,u>
+; CHECK-NEXT: jmp .LBB0_1
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_2: # %forbody
+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: shlq $4, %rcx
+; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: movdqa (%rdx,%rcx), %xmm1
+; CHECK-NEXT: pslld $2, %xmm1
+; CHECK-NEXT: psubd %xmm0, %xmm1
+; CHECK-NEXT: pextrd $2, %xmm1, 8(%rax,%rcx)
+; CHECK-NEXT: movq %xmm1, (%rax,%rcx)
+; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: .LBB0_1: # %forcond
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: jl .LBB0_2
+; CHECK-NEXT: # BB#3: # %afterfor
+; CHECK-NEXT: retq
entry:
- %dst.addr = alloca <3 x i32>* ; <<3 x i32>**> [#uses=2]
- %src.addr = alloca <3 x i32>* ; <<3 x i32>**> [#uses=2]
- %n.addr = alloca i32 ; <i32*> [#uses=2]
- %v = alloca <3 x i32>, align 16 ; <<3 x i32>*> [#uses=1]
- %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ %dst.addr = alloca <3 x i32>*
+ %src.addr = alloca <3 x i32>*
+ %n.addr = alloca i32
+ %v = alloca <3 x i32>, align 16
+ %i = alloca i32, align 4
store <3 x i32>* %dst, <3 x i32>** %dst.addr
store <3 x i32>* %src, <3 x i32>** %src.addr
store i32 %n, i32* %n.addr
@@ -19,32 +48,32 @@ entry:
store i32 0, i32* %i
br label %forcond
-forcond: ; preds = %forinc, %entry
- %tmp = load i32, i32* %i ; <i32> [#uses=1]
- %tmp1 = load i32, i32* %n.addr ; <i32> [#uses=1]
- %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+forcond:
+ %tmp = load i32, i32* %i
+ %tmp1 = load i32, i32* %n.addr
+ %cmp = icmp slt i32 %tmp, %tmp1
br i1 %cmp, label %forbody, label %afterfor
-forbody: ; preds = %forcond
- %tmp2 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp3 = load <3 x i32>*, <3 x i32>** %dst.addr ; <<3 x i32>*> [#uses=1]
- %arrayidx = getelementptr <3 x i32>, <3 x i32>* %tmp3, i32 %tmp2 ; <<3 x i32>*> [#uses=1]
- %tmp4 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp5 = load <3 x i32>*, <3 x i32>** %src.addr ; <<3 x i32>*> [#uses=1]
- %arrayidx6 = getelementptr <3 x i32>, <3 x i32>* %tmp5, i32 %tmp4 ; <<3 x i32>*> [#uses=1]
- %tmp7 = load <3 x i32>, <3 x i32>* %arrayidx6 ; <<3 x i32>> [#uses=1]
- %mul = mul <3 x i32> %tmp7, < i32 4, i32 4, i32 4 > ; <<3 x i32>> [#uses=1]
- %sub = sub <3 x i32> %mul, < i32 3, i32 3, i32 3 > ; <<3 x i32>> [#uses=1]
+forbody:
+ %tmp2 = load i32, i32* %i
+ %tmp3 = load <3 x i32>*, <3 x i32>** %dst.addr
+ %arrayidx = getelementptr <3 x i32>, <3 x i32>* %tmp3, i32 %tmp2
+ %tmp4 = load i32, i32* %i
+ %tmp5 = load <3 x i32>*, <3 x i32>** %src.addr
+ %arrayidx6 = getelementptr <3 x i32>, <3 x i32>* %tmp5, i32 %tmp4
+ %tmp7 = load <3 x i32>, <3 x i32>* %arrayidx6
+ %mul = mul <3 x i32> %tmp7, < i32 4, i32 4, i32 4 >
+ %sub = sub <3 x i32> %mul, < i32 3, i32 3, i32 3 >
store <3 x i32> %sub, <3 x i32>* %arrayidx
br label %forinc
-forinc: ; preds = %forbody
- %tmp8 = load i32, i32* %i ; <i32> [#uses=1]
- %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+forinc:
+ %tmp8 = load i32, i32* %i
+ %inc = add i32 %tmp8, 1
store i32 %inc, i32* %i
br label %forcond
-afterfor: ; preds = %forcond
+afterfor:
ret void
}
Modified: llvm/trunk/test/CodeGen/X86/widen_arith-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-6.ll?rev=305656&r1=305655&r2=305656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_arith-6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_arith-6.ll Sun Jun 18 16:48:44 2017
@@ -1,16 +1,50 @@
-; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
-; CHECK: mulps
-; CHECK: addps
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s
; widen a v3f32 to vfi32 to do a vector multiple and an add
define void @update(<3 x float>* %dst, <3 x float>* %src, i32 %n) nounwind {
+; CHECK-LABEL: update:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: pushl %ebp
+; CHECK-NEXT: movl %esp, %ebp
+; CHECK-NEXT: andl $-16, %esp
+; CHECK-NEXT: subl $48, %esp
+; CHECK-NEXT: movl $1077936128, {{[0-9]+}}(%esp) # imm = 0x40400000
+; CHECK-NEXT: movl $1073741824, {{[0-9]+}}(%esp) # imm = 0x40000000
+; CHECK-NEXT: movl $1065353216, {{[0-9]+}}(%esp) # imm = 0x3F800000
+; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1976.04004,1976.04004,1976.04004,u>
+; CHECK-NEXT: jmp .LBB0_1
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_2: # %forbody
+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl 8(%ebp), %ecx
+; CHECK-NEXT: shll $4, %eax
+; CHECK-NEXT: movl 12(%ebp), %edx
+; CHECK-NEXT: movaps (%edx,%eax), %xmm1
+; CHECK-NEXT: mulps {{[0-9]+}}(%esp), %xmm1
+; CHECK-NEXT: addps %xmm0, %xmm1
+; CHECK-NEXT: extractps $2, %xmm1, 8(%ecx,%eax)
+; CHECK-NEXT: extractps $1, %xmm1, 4(%ecx,%eax)
+; CHECK-NEXT: movss %xmm1, (%ecx,%eax)
+; CHECK-NEXT: incl {{[0-9]+}}(%esp)
+; CHECK-NEXT: .LBB0_1: # %forcond
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: cmpl 16(%ebp), %eax
+; CHECK-NEXT: jl .LBB0_2
+; CHECK-NEXT: # BB#3: # %afterfor
+; CHECK-NEXT: movl %ebp, %esp
+; CHECK-NEXT: popl %ebp
+; CHECK-NEXT: retl
entry:
- %dst.addr = alloca <3 x float>* ; <<3 x float>**> [#uses=2]
- %src.addr = alloca <3 x float>* ; <<3 x float>**> [#uses=2]
- %n.addr = alloca i32 ; <i32*> [#uses=2]
- %v = alloca <3 x float>, align 16 ; <<3 x float>*> [#uses=2]
- %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ %dst.addr = alloca <3 x float>*
+ %src.addr = alloca <3 x float>*
+ %n.addr = alloca i32
+ %v = alloca <3 x float>, align 16
+ %i = alloca i32, align 4
store <3 x float>* %dst, <3 x float>** %dst.addr
store <3 x float>* %src, <3 x float>** %src.addr
store i32 %n, i32* %n.addr
@@ -18,32 +52,32 @@ entry:
store i32 0, i32* %i
br label %forcond
-forcond: ; preds = %forinc, %entry
- %tmp = load i32, i32* %i ; <i32> [#uses=1]
- %tmp1 = load i32, i32* %n.addr ; <i32> [#uses=1]
- %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+forcond:
+ %tmp = load i32, i32* %i
+ %tmp1 = load i32, i32* %n.addr
+ %cmp = icmp slt i32 %tmp, %tmp1
br i1 %cmp, label %forbody, label %afterfor
-forbody: ; preds = %forcond
- %tmp2 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp3 = load <3 x float>*, <3 x float>** %dst.addr ; <<3 x float>*> [#uses=1]
- %arrayidx = getelementptr <3 x float>, <3 x float>* %tmp3, i32 %tmp2 ; <<3 x float>*> [#uses=1]
- %tmp4 = load i32, i32* %i ; <i32> [#uses=1]
- %tmp5 = load <3 x float>*, <3 x float>** %src.addr ; <<3 x float>*> [#uses=1]
- %arrayidx6 = getelementptr <3 x float>, <3 x float>* %tmp5, i32 %tmp4 ; <<3 x float>*> [#uses=1]
- %tmp7 = load <3 x float>, <3 x float>* %arrayidx6 ; <<3 x float>> [#uses=1]
- %tmp8 = load <3 x float>, <3 x float>* %v ; <<3 x float>> [#uses=1]
- %mul = fmul <3 x float> %tmp7, %tmp8 ; <<3 x float>> [#uses=1]
- %add = fadd <3 x float> %mul, < float 0x409EE02900000000, float 0x409EE02900000000, float 0x409EE02900000000 > ; <<3 x float>> [#uses=1]
+forbody:
+ %tmp2 = load i32, i32* %i
+ %tmp3 = load <3 x float>*, <3 x float>** %dst.addr
+ %arrayidx = getelementptr <3 x float>, <3 x float>* %tmp3, i32 %tmp2
+ %tmp4 = load i32, i32* %i
+ %tmp5 = load <3 x float>*, <3 x float>** %src.addr
+ %arrayidx6 = getelementptr <3 x float>, <3 x float>* %tmp5, i32 %tmp4
+ %tmp7 = load <3 x float>, <3 x float>* %arrayidx6
+ %tmp8 = load <3 x float>, <3 x float>* %v
+ %mul = fmul <3 x float> %tmp7, %tmp8
+ %add = fadd <3 x float> %mul, < float 0x409EE02900000000, float 0x409EE02900000000, float 0x409EE02900000000 >
store <3 x float> %add, <3 x float>* %arrayidx
br label %forinc
-forinc: ; preds = %forbody
- %tmp9 = load i32, i32* %i ; <i32> [#uses=1]
- %inc = add i32 %tmp9, 1 ; <i32> [#uses=1]
+forinc:
+ %tmp9 = load i32, i32* %i
+ %inc = add i32 %tmp9, 1
store i32 %inc, i32* %i
br label %forcond
-afterfor: ; preds = %forcond
+afterfor:
ret void
}
More information about the llvm-commits
mailing list