[PATCH] D34314: [PPC] Remove isBarrier from CFENCE8's definition.

[Tim Shen via Phabricator via llvm-commits]

timshen created this revision.
Herald added subscribers: hiraditya, nemanjai, sanjoy.

This is my misunderstanding on isBarrier. It's not for memory barriers,
but for other control flow purposes. lwsync doesn't have it either.

This fixes a simple crash with -verify-machineinstrs like below:

  define void @Foo() {
  entry:
    %tmp = load atomic i64, i64* undef acquire, align 8
    unreachable
  }

I deliberately don't want to check in the test, since there is little
chance to regress on such a mistake. Such a test adds noise to the code
base.

I plan to check in first, since it fixes a crash, and the fix is obvious.


https://reviews.llvm.org/D34314

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td


Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -994,7 +994,7 @@
                           (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
                  isPPC64;
 
-let isBarrier = 1, isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
+let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
 def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
 
 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),


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