[PATCH] D34220: [AArch64] Prefer B.cond to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free"

Chad Rosier via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 15 12:12:52 PDT 2017


mcrosier added a comment.

In https://reviews.llvm.org/D34220#781506, @MatzeB wrote:

> - The transformation make sense to me.


Great! :D

> - Does this need to be a separate pass? Glancing at the code, it seems that performBRCONDCombine() in AArch64ISelLowering.cpp is the only place creating CBZ instructions (except for FastISel). So maybe the adjustment can be performed there?

Initially, I attempted this during ISel but ran into several problems.  First, I found myself duplicating a lot of code from AArch64ISelDAGtoDAG.cpp to avoid this transformation when the 'AND' could be folded into a bitfield insert/extract operation (e.g., BFM).  It also leads to the aforementioned problems (i.e., the ConditionalCompares pass would need to be able to support ANDS, BICS and we might miss MADD fusion opportunities because we can't fuse MUL+ADDS).

> - The code has a lot of opcode "tables" (in the form of switch/case). It's a judgement call each time, but generally I think it looks better if we have most opcode based tables in AArch64InstrInfo. At least the part mapping "S" opcodes to the non-"S" opcodes looks like a good candidate.

I'm happy to move the large opcode table to switch between the non-flag-setting to flag-setting opcodes.  No problem.


https://reviews.llvm.org/D34220





More information about the llvm-commits mailing list