[PATCH] D34189: AMDGPU: Avoid saving/restoring reserved m0 register

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

For the record: I just checked why that testcase did not fail before my patch. It's simply hitting a bug in the register scavenger:

  $ llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -print-machineinstrs test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
  ...
  # After Shrink Wrapping analysis:
  # Machine code for function max_12_sgprs_14_input_sgprs: NoPHIs, TracksLiveness, NoVRegs
  ...
  BB#1:
    ...%SGPR4_SGPR5<def> = SI_SPILL_S64_RESTORE <fi#3>, %EXEC<imp-use>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use>, %SGPR7<imp-use>, %M0<imp-def>; mem:LD8[FixedStack3](align=4)

after frame elimination/scavenging:

  ...
  # After Prologue/Epilogue Insertion & Frame Finalization:
  # Machine code for function max_12_sgprs_14_input_sgprs: NoPHIs, TracksLiveness, NoVRegs
  ...
  #B1:
    ...
      %M0<def> = S_ADD_U32 %SGPR7, 1024, %SCC<imp-def>
      %SGPR4_SGPR5<def> = S_BUFFER_LOAD_DWORDX2_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %M0<kill>, 0; mem:LD8[FixedStack3](align=4)
      %M0<def> = COPY %SGPR4<kill>



> This restores the wrong value into M0. (There is not free register at that point in the program so your recovery strategy of saving M0 in a register is impossible to solve at that point, but you happen to hit a bug in the old scavenging code that reports SGPR4 :-/ )
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Repository:
  rL LLVM

https://reviews.llvm.org/D34189