[PATCH] D34208: [PowerPC] fix potential verification errors on CFENCE8

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs created this revision.

This patch fixes a potential verification error (64-bit register operands for cmpw)  with `-verify-machineinstrs` while expanding CFENCE8 into cmp + bc + isync.
As far as I read the references, we can use cmpd (or any compare instruction) for this purpose.
http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html


https://reviews.llvm.org/D34208

Files:
  lib/Target/PowerPC/PPCInstrInfo.cpp


Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1964,7 +1964,7 @@
   }
   case PPC::CFENCE8: {
     auto Val = MI.getOperand(0).getReg();
-    BuildMI(MBB, MI, DL, get(PPC::CMPW), PPC::CR7).addReg(Val).addReg(Val);
+    BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
     BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
         .addImm(PPC::PRED_NE_MINUS)
         .addReg(PPC::CR7)


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