[llvm] r305382 - [mips] Fix machine verifier errors in the long branch pass
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 05:16:47 PDT 2017
Author: sdardis
Date: Wed Jun 14 07:16:47 2017
New Revision: 305382
URL: http://llvm.org/viewvc/llvm-project?rev=305382&view=rev
Log:
[mips] Fix machine verifier errors in the long branch pass
This patch fixes two systemic machine verifier errors in the long
branch pass. The first is the incorrect basic block successors
and the second was the incorrect construction of several jump
instructions.
This partially resolves PR27458 and the associated PR32146.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D33378
Modified:
llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
llvm/trunk/test/CodeGen/Mips/longbranch.ll
Modified: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp?rev=305382&r1=305381&r2=305382&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp Wed Jun 14 07:16:47 2017
@@ -274,8 +274,8 @@ void MipsLongBranch::expandToLongBranch(
if (IsPIC) {
MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
MF->insert(FallThroughMBB, BalTgtMBB);
- LongBrMBB->addSuccessor(BalTgtMBB);
- BalTgtMBB->addSuccessor(TgtMBB);
+ LongBrMBB->addSuccessor(BalTgtMBB, BranchProbability::getOne());
+ BalTgtMBB->addSuccessor(&*FallThroughMBB, BranchProbability::getOne());
// We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
// instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
@@ -342,8 +342,8 @@ void MipsLongBranch::expandToLongBranch(
.addReg(Mips::SP).addImm(8);
if (Subtarget.hasMips32r6())
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR))
- .addReg(Mips::ZERO).addReg(Mips::AT);
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR), Mips::ZERO)
+ .addReg(Mips::AT);
else
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
@@ -415,8 +415,8 @@ void MipsLongBranch::expandToLongBranch(
.addReg(Mips::SP_64).addImm(0);
if (Subtarget.hasMips64r6())
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR64))
- .addReg(Mips::ZERO_64).addReg(Mips::AT_64);
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR64), Mips::ZERO_64)
+ .addReg(Mips::AT_64);
else
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
Modified: llvm/trunk/test/CodeGen/Mips/longbranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch.ll?rev=305382&r1=305381&r2=305382&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch.ll Wed Jun 14 07:16:47 2017
@@ -1,17 +1,17 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \
+; RUN: llc -march=mipsel -relocation-model=pic < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs \
; RUN: | FileCheck %s -check-prefix=O32
; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \
-; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6
+; RUN: -relocation-model=pic -asm-show-inst < %s -verify-machineinstrs | FileCheck %s -check-prefix=O32-R6
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
-; RUN: < %s | FileCheck %s -check-prefix=N64
+; RUN: < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
-; RUN: < %s | FileCheck %s -check-prefix=N64
+; RUN: < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64
; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \
-; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6
+; RUN: -relocation-model=pic -asm-show-inst < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64-R6
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \
-; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS
-; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \
+; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs | FileCheck %s -check-prefix=MICROMIPS
+; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs \
; RUN: | FileCheck %s -check-prefix=NACL
@@ -59,9 +59,9 @@ end:
; Check for long branch expansion:
; O32: addiu $sp, $sp, -8
; O32-NEXT: sw $ra, 0($sp)
-; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; O32-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]]))
; O32-NEXT: bal $[[BB1]]
-; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; O32-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]]))
; O32-NEXT: $[[BB1]]:
; O32-NEXT: addu $1, $ra, $1
; O32-NEXT: lw $ra, 0($sp)
@@ -72,7 +72,7 @@ end:
; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; O32: addiu $[[R2:[0-9]+]], $zero, 1
; O32: sw $[[R2]], 0($[[R1]])
-; O32: $[[BB2]]:
+; O32: # BB#[[BB2]]:
; O32: jr $ra
; O32: nop
@@ -90,10 +90,10 @@ end:
; Check for long branch expansion:
; N64: daddiu $sp, $sp, -16
; N64-NEXT: sd $ra, 0($sp)
-; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]])
+; N64-NEXT: daddiu $1, $zero, %hi(.LBB0_[[BB2:[0-9_]+]]-[[BB1:\.LBB[0-9_]+]])
; N64-NEXT: dsll $1, $1, 16
; N64-NEXT: bal [[BB1]]
-; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]])
+; N64-NEXT: daddiu $1, $1, %lo(.LBB0_[[BB2]]-[[BB1]])
; N64-NEXT: [[BB1]]:
; N64-NEXT: daddu $1, $ra, $1
; N64-NEXT: ld $ra, 0($sp)
@@ -105,7 +105,7 @@ end:
; N64: addiu $[[R3:[0-9]+]], $zero, 1
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
; N64: sw $[[R3]], 0($[[R2]])
-; N64: [[BB2]]:
+; N64: # BB#[[BB2]]:
; N64: jr $ra
; N64: nop
@@ -125,9 +125,9 @@ end:
; Check for long branch expansion:
; MICROMIPS: addiu $sp, $sp, -8
; MICROMIPS-NEXT: sw $ra, 0($sp)
-; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; MICROMIPS-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]]))
; MICROMIPS-NEXT: bal $[[BB1]]
-; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; MICROMIPS-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]]))
; MICROMIPS-NEXT: $[[BB1]]:
; MICROMIPS-NEXT: addu $1, $ra, $1
; MICROMIPS-NEXT: lw $ra, 0($sp)
@@ -138,7 +138,7 @@ end:
; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; MICROMIPS: li16 $[[R2:[0-9]+]], 1
; MICROMIPS: sw16 $[[R2]], 0($[[R1]])
-; MICROMIPS: $[[BB2]]:
+; MICROMIPS: # BB#[[BB2]]:
; MICROMIPS: jrc $ra
@@ -154,9 +154,9 @@ end:
; Check for long branch expansion:
; NACL: addiu $sp, $sp, -8
; NACL-NEXT: sw $ra, 0($sp)
-; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; NACL-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]]))
; NACL-NEXT: bal $[[BB1]]
-; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; NACL-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]]))
; NACL-NEXT: $[[BB1]]:
; NACL-NEXT: addu $1, $ra, $1
; NACL-NEXT: lw $ra, 0($sp)
@@ -169,7 +169,7 @@ end:
; NACL: addiu $[[R2:[0-9]+]], $zero, 1
; NACL: sw $[[R2]], 0($[[R1]])
; NACL: .p2align 4
-; NACL-NEXT: $[[BB2]]:
+; NACL-NEXT: # BB#[[BB2]]:
; NACL: jr $ra
; NACL: nop
}
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