[PATCH] D34189: AMDGPU: Avoid saving/restoring reserved m0 register

[Matthias Braun via Phabricator via llvm-commits]

MatzeB created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, mcrosier, qcolombet.

This is in preparation to https://reviews.llvm.org/D23097 which uncovered some problems in the way AMDGPU uses the register scavenger in SIRegisterInfo::spillSGPR()/SIRegisterInfo::restoreSGPR().

- The current code does not use the register scavenger correctly:
  - RS->isRegUsed() always reports true for m0 because it is a reserved register.
  - Even if m0 was not reserved RS->isRegUsed() would give you information about the position where we are scavenging a register. This is not actually the position where the spill/reload will be inserted.
  - Spilling m0 creates a new vreg. This is sketchy as that happens at a time when the register scavenger is already spilling/reloading to free registers for vreg assignment. If there is no free physreg at that place we end up in an endless loop (because m0 is always reported as reserved, see above). The existing tests are lucky to not hit the case with https://reviews.llvm.org/D23097 applied one is hit.

This changes the code to assume that m0 is available since it is
reserved so we shouldn't have any longer liveranges crossing potential
spill/reload places.


Repository:
  rL LLVM

https://reviews.llvm.org/D34189

Files:
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/spill-m0.ll


Index: test/CodeGen/AMDGPU/spill-m0.ll
===================================================================
--- test/CodeGen/AMDGPU/spill-m0.ll
+++ test/CodeGen/AMDGPU/spill-m0.ll
@@ -119,10 +119,8 @@
 
 ; GCN: ; clobber m0
 
-; TOSMEM: s_mov_b32 vcc_hi, m0
 ; TOSMEM: s_add_u32 m0, s3, 0x100
 ; TOSMEM-NEXT: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Spill
-; TOSMEM: s_mov_b32 m0, vcc_hi
 
 ; TOSMEM: s_mov_b64 exec,
 ; TOSMEM: s_cbranch_execz
@@ -170,10 +168,8 @@
 
 ; TOSMEM: s_mov_b32 m0, -1
 
-; TOSMEM: s_mov_b32 vcc_hi, m0
 ; TOSMEM: s_add_u32 m0, s3, 0x100
 ; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload
-; TOSMEM: s_mov_b32 m0, vcc_hi
 ; TOSMEM: s_waitcnt lgkmcnt(0)
 
 ; TOSMEM: ds_write_b64
Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -631,16 +631,8 @@
 
   assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
 
+  assert(MRI.isReserved(AMDGPU::M0));
   unsigned OffsetReg = AMDGPU::M0;
-  unsigned M0CopyReg = AMDGPU::NoRegister;
-
-  if (SpillToSMEM) {
-    if (RS->isRegUsed(AMDGPU::M0)) {
-      M0CopyReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
-      BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg)
-        .addReg(AMDGPU::M0);
-    }
-  }
 
   unsigned ScalarStoreOp;
   unsigned EltSize = 4;
@@ -754,11 +746,6 @@
     }
   }
 
-  if (M0CopyReg != AMDGPU::NoRegister) {
-    BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(M0CopyReg, RegState::Kill);
-  }
-
   MI->eraseFromParent();
   MFI->addToSpilledSGPRs(NumSubRegs);
   return true;
@@ -791,16 +778,8 @@
 
   assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
 
+  assert(MRI.isReserved(AMDGPU::M0));
   unsigned OffsetReg = AMDGPU::M0;
-  unsigned M0CopyReg = AMDGPU::NoRegister;
-
-  if (SpillToSMEM) {
-    if (RS->isRegUsed(AMDGPU::M0)) {
-      M0CopyReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
-      BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg)
-        .addReg(AMDGPU::M0);
-    }
-  }
 
   unsigned EltSize = 4;
   unsigned ScalarLoadOp;
@@ -898,11 +877,6 @@
     }
   }
 
-  if (M0CopyReg != AMDGPU::NoRegister) {
-    BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(M0CopyReg, RegState::Kill);
-  }
-
   MI->eraseFromParent();
   return true;
 }


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