[llvm] r305305 - [Hexagon] Generate store-immediate instructions for stack objects
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 10:10:16 PDT 2017
Author: kparzysz
Date: Tue Jun 13 12:10:16 2017
New Revision: 305305
URL: http://llvm.org/viewvc/llvm-project?rev=305305&view=rev
Log:
[Hexagon] Generate store-immediate instructions for stack objects
Store-immediate instructions have a non-extendable offset. Since the
actual offset for a stack object is not known until much later, only
generate these stores when the stack size (at the time of instruction
selection) is small.
Added:
llvm/trunk/test/CodeGen/Hexagon/store-imm-stack-object.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=305305&r1=305304&r2=305305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Jun 13 12:10:16 2017
@@ -124,6 +124,7 @@ private:
bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
bool isOrEquivalentToAdd(const SDNode *N) const;
bool isAlignedMemNode(const MemSDNode *N) const;
+ bool isSmallStackStore(const StoreSDNode *N) const;
bool isPositiveHalfWord(const SDNode *N) const;
// DAG preprocessing functions.
@@ -1462,6 +1463,20 @@ bool HexagonDAGToDAGISel::isAlignedMemNo
return N->getAlignment() >= N->getMemoryVT().getStoreSize();
}
+bool HexagonDAGToDAGISel::isSmallStackStore(const StoreSDNode *N) const {
+ unsigned StackSize = MF->getFrameInfo().estimateStackSize(*MF);
+ switch (N->getMemoryVT().getStoreSize()) {
+ case 1:
+ return StackSize <= 56; // 1*2^6 - 8
+ case 2:
+ return StackSize <= 120; // 2*2^6 - 8
+ case 4:
+ return StackSize <= 248; // 4*2^6 - 8
+ default:
+ return false;
+ }
+}
+
// Return true when the given node fits in a positive half word.
bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const {
if (const ConstantSDNode *CN = dyn_cast<const ConstantSDNode>(N)) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=305305&r1=305304&r2=305305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue Jun 13 12:10:16 2017
@@ -1475,16 +1475,22 @@ def i32in8ImmPred: PatLeaf<(i32 imm), [{
return v == (int64_t)(int8_t)v;
}]>;
+class SmallStackStore<PatFrag Store>
+ : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{
+ return isSmallStackStore(cast<StoreSDNode>(N));
+}]>;
let AddedComplexity = 40 in {
// Even though the offset is not extendable in the store-immediate, we
// can still generate the fi# in the base address. If the final offset
// is not valid for the instruction, we will replace it with a scratch
// register.
-// def: Storexm_fi_pat <truncstorei8, s32_0ImmPred, ToImmByte, S4_storeirb_io>;
-// def: Storexm_fi_pat <truncstorei16, i16in8ImmPred, ToImmHalf,
-// S4_storeirh_io>;
-// def: Storexm_fi_pat <store, i32in8ImmPred, ToImmWord, S4_storeiri_io>;
+ def: Storexm_fi_pat <SmallStackStore<truncstorei8>, s32_0ImmPred,
+ ToImmByte, S4_storeirb_io>;
+ def: Storexm_fi_pat <SmallStackStore<truncstorei16>, i16in8ImmPred,
+ ToImmHalf, S4_storeirh_io>;
+ def: Storexm_fi_pat <SmallStackStore<store>, i32in8ImmPred,
+ ToImmWord, S4_storeiri_io>;
// defm: Storexm_fi_add_pat <truncstorei8, s32_0ImmPred, u6_0ImmPred, ToImmByte,
// S4_storeirb_io>;
Added: llvm/trunk/test/CodeGen/Hexagon/store-imm-stack-object.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/store-imm-stack-object.ll?rev=305305&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/store-imm-stack-object.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/store-imm-stack-object.ll Tue Jun 13 12:10:16 2017
@@ -0,0 +1,86 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon"
+
+; CHECK-LABEL: test1:
+; CHECK: [[REG1:(r[0-9]+)]] = ##875770417
+; CHECK-DAG: memw(r29+#4) = [[REG1]]
+; CHECK-DAG: memw(r29+#8) = #51
+; CHECK-DAG: memh(r29+#12) = #50
+; CHECK-DAG: memb(r29+#15) = #49
+define void @test1() {
+b0:
+ %v1 = alloca [1 x i8], align 1
+ %v2 = alloca i16, align 2
+ %v3 = alloca i32, align 4
+ %v4 = alloca i32, align 4
+ %v5 = getelementptr inbounds [1 x i8], [1 x i8]* %v1, i32 0, i32 0
+ call void @llvm.lifetime.start(i64 1, i8* %v5)
+ store i8 49, i8* %v5, align 1
+ %v6 = bitcast i16* %v2 to i8*
+ call void @llvm.lifetime.start(i64 2, i8* %v6)
+ store i16 50, i16* %v2, align 2
+ %v7 = bitcast i32* %v3 to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %v7)
+ store i32 51, i32* %v3, align 4
+ %v8 = bitcast i32* %v4 to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %v8)
+ store i32 875770417, i32* %v4, align 4
+ call void @test4(i8* %v5, i8* %v6, i8* %v7, i8* %v8)
+ call void @llvm.lifetime.end(i64 4, i8* %v8)
+ call void @llvm.lifetime.end(i64 4, i8* %v7)
+ call void @llvm.lifetime.end(i64 2, i8* %v6)
+ call void @llvm.lifetime.end(i64 1, i8* %v5)
+ ret void
+}
+
+; CHECK-LABEL: test2:
+; CHECK-DAG: memw(r29+#208) = #51
+; CHECK-DAG: memh(r29+#212) = r{{[0-9]+}}
+; CHECK-DAG: memb(r29+#215) = r{{[0-9]+}}
+define void @test2() {
+b0:
+ %v1 = alloca [1 x i8], align 1
+ %v2 = alloca i16, align 2
+ %v3 = alloca i32, align 4
+ %v4 = alloca i32, align 4
+ %v5 = alloca [100 x i8], align 8
+ %v6 = alloca [101 x i8], align 8
+ %v7 = getelementptr inbounds [1 x i8], [1 x i8]* %v1, i32 0, i32 0
+ call void @llvm.lifetime.start(i64 1, i8* %v7)
+ store i8 49, i8* %v7, align 1
+ %v8 = bitcast i16* %v2 to i8*
+ call void @llvm.lifetime.start(i64 2, i8* %v8)
+ store i16 50, i16* %v2, align 2
+ %v9 = bitcast i32* %v3 to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %v9)
+ store i32 51, i32* %v3, align 4
+ %v10 = bitcast i32* %v4 to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %v10)
+ store i32 875770417, i32* %v4, align 4
+ %v11 = getelementptr inbounds [100 x i8], [100 x i8]* %v5, i32 0, i32 0
+ call void @llvm.lifetime.start(i64 100, i8* %v11)
+ call void @llvm.memset.p0i8.i32(i8* %v11, i8 0, i32 100, i32 8, i1 false)
+ store i8 50, i8* %v11, align 8
+ %v12 = getelementptr inbounds [101 x i8], [101 x i8]* %v6, i32 0, i32 0
+ call void @llvm.lifetime.start(i64 101, i8* %v12)
+ call void @llvm.memset.p0i8.i32(i8* %v12, i8 0, i32 101, i32 8, i1 false)
+ store i8 49, i8* %v12, align 8
+ call void @test3(i8* %v7, i8* %v8, i8* %v9, i8* %v10, i8* %v11, i8* %v12)
+ call void @llvm.lifetime.end(i64 101, i8* %v12)
+ call void @llvm.lifetime.end(i64 100, i8* %v11)
+ call void @llvm.lifetime.end(i64 4, i8* %v10)
+ call void @llvm.lifetime.end(i64 4, i8* %v9)
+ call void @llvm.lifetime.end(i64 2, i8* %v8)
+ call void @llvm.lifetime.end(i64 1, i8* %v7)
+ ret void
+}
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #0
+declare void @llvm.lifetime.end(i64, i8* nocapture) #0
+declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i32, i1) #0
+
+declare void @test3(i8*, i8*, i8*, i8*, i8*, i8*)
+declare void @test4(i8*, i8*, i8*, i8*)
+
+attributes #0 = { argmemonly nounwind "target-cpu"="hexagonv60" }
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