[llvm] r305302 - [Hexagon] Generate multiply-high instruction in isel

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Jun 13 11:21:57 2017
New Revision: 305302

URL: http://llvm.org/viewvc/llvm-project?rev=305302&view=rev
Log:
[Hexagon] Generate multiply-high instruction in isel

Added:
    llvm/trunk/test/CodeGen/Hexagon/mulh.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=305302&r1=305301&r2=305302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue Jun 13 11:21:57 2017
@@ -401,6 +401,11 @@ def Aext64: PatFrag<(ops node:$Rs), (i64
 def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
 def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
 
+def: Pat<(i32 (trunc (sra (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(i32 (trunc (srl (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+
 def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
          (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
 

Added: llvm/trunk/test/CodeGen/Hexagon/mulh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mulh.ll?rev=305302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mulh.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/mulh.ll Tue Jun 13 11:21:57 2017
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon"
+
+; CHECK-LABEL: danny:
+; CHECK: r{{[0-9]+}} = mpy(r0,r1)  
+define i32 @danny(i32 %a0, i32 %a1) {
+b2:
+  %v3 = sext i32 %a0 to i64
+  %v4 = sext i32 %a1 to i64
+  %v5 = mul nsw i64 %v3, %v4
+  %v6 = ashr i64 %v5, 32
+  %v7 = trunc i64 %v6 to i32
+  ret i32 %v7
+}
+
+; CHECK-LABEL: sammy:
+; CHECK: r{{[0-9]+}} = mpy(r0,r1)
+define i32 @sammy(i32 %a0, i32 %a1) {
+b2:
+  %v3 = sext i32 %a0 to i64
+  %v4 = sext i32 %a1 to i64
+  %v5 = mul nsw i64 %v3, %v4
+  %v6 = lshr i64 %v5, 32
+  %v7 = trunc i64 %v6 to i32
+  ret i32 %v7
+}