[PATCH] D34088: [DAGCombine] Make sure we check the ResNo from UADDO before combining
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 11 04:37:16 PDT 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL305162: [DAGCombine] Make sure we check the ResNo from UADDO before combining (authored by deadalnix).
Changed prior to commit:
https://reviews.llvm.org/D34088?vs=102131&id=102132#toc
Repository:
rL LLVM
https://reviews.llvm.org/D34088
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/addcarry.ll
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2217,7 +2217,8 @@
SDNode *N) {
// Iff the flag result is dead:
// (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
- if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::UADDO) &&
+ if ((N0.getOpcode() == ISD::ADD ||
+ (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) &&
isNullConstant(N1) && !N->hasAnyUseOfValue(1))
return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
N0.getOperand(0), N0.getOperand(1), CarryIn);
Index: llvm/trunk/test/CodeGen/X86/addcarry.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/addcarry.ll
+++ llvm/trunk/test/CodeGen/X86/addcarry.ll
@@ -81,6 +81,30 @@
ret void
}
+define i8 @e(i32* nocapture %a, i32 %b) nounwind {
+; CHECK-LABEL: e:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; CHECK-NEXT: movl (%rdi), %ecx
+; CHECK-NEXT: leal (%rsi,%rcx), %edx
+; CHECK-NEXT: addl %esi, %edx
+; CHECK-NEXT: setb %al
+; CHECK-NEXT: addl %esi, %ecx
+; CHECK-NEXT: movl %edx, (%rdi)
+; CHECK-NEXT: adcb $0, %al
+; CHECK-NEXT: retq
+ %1 = load i32, i32* %a, align 4
+ %2 = add i32 %1, %b
+ %3 = icmp ult i32 %2, %b
+ %4 = zext i1 %3 to i8
+ %5 = add i32 %2, %b
+ store i32 %5, i32* %a, align 4
+ %6 = icmp ult i32 %5, %b
+ %7 = zext i1 %6 to i8
+ %8 = add nuw nsw i8 %7, %4
+ ret i8 %8
+}
+
%scalar = type { [4 x i64] }
define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) {
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