[PATCH] D34077: DAGCombine: Combine BUILD_VECTOR to TRUNCATE

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

A few minors, but would like to see ARM fixed first.



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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:14262
+    return SDValue();
+
+  // Compute the stride from the first index.
----------------
Would it be useful to support BUILD_VECTORs containing UNDEF elements?


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:14272
+      (VT.getScalarSizeInBits() * Stride > 64))
+    return SDValue();
+
----------------
Check for ISD::TRUNCATE legality, this might even help ARM?


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Comment at: test/CodeGen/ARM/vext.ll:205
 ; CHECK-NEXT:    vzip.16 d17, d16
-; CHECK-NEXT:    vmov  r0, r1, d17
+; CHECK-NEXT:    vmov r0, r1, d17
 ; CHECK-NEXT:    mov pc, lr
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whitespace only change - if this is actually relevant commit it separately now as a NFC, else discard it.


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Comment at: test/CodeGen/X86/shuffle-vs-trunc-256.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512F
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Ideally it'd be good to see the codegen for AVX1 targets as well


https://reviews.llvm.org/D34077