[llvm] r305016 - RegAllocPBQP: Do not assign reserved physical register
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 8 14:30:54 PDT 2017
Author: matze
Date: Thu Jun 8 16:30:54 2017
New Revision: 305016
URL: http://llvm.org/viewvc/llvm-project?rev=305016&view=rev
Log:
RegAllocPBQP: Do not assign reserved physical register
(0) RegAllocPBQP: Since getRawAllocationOrder() may return a collection that includes reserved physical registers, iterate to find an un-reserved physical register.
(1) VirtRegMap: Enforce the invariant: "no reserved physical registers" in assignVirt2Phys(). Previously, this was checked only after the fact in VirtRegRewriter::rewrite.
(2) MachineVerifier: updated the test per MatzeB's review.
(3) +testcase
Patch by Nick Johnson<Nicholas.Paul.Johnson at deshawresearch.com>!
Differential Revision: https://reviews.llvm.org/D33947
Added:
llvm/trunk/test/CodeGen/Mips/pbqp-reserved-physreg.ll
Modified:
llvm/trunk/include/llvm/CodeGen/VirtRegMap.h
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
Modified: llvm/trunk/include/llvm/CodeGen/VirtRegMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/VirtRegMap.h?rev=305016&r1=305015&r2=305016&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/VirtRegMap.h (original)
+++ llvm/trunk/include/llvm/CodeGen/VirtRegMap.h Thu Jun 8 16:30:54 2017
@@ -102,14 +102,7 @@ namespace llvm {
/// @brief creates a mapping for the specified virtual register to
/// the specified physical register
- void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
- assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
- TargetRegisterInfo::isPhysicalRegister(physReg));
- assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
- "attempt to assign physical register to already mapped "
- "virtual register");
- Virt2PhysMap[virtReg] = physReg;
- }
+ void assignVirt2Phys(unsigned virtReg, MCPhysReg physReg);
/// @brief clears the specified virtual register's, physical
/// register mapping
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=305016&r1=305015&r2=305016&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Jun 8 16:30:54 2017
@@ -945,7 +945,6 @@ void MachineVerifier::visitMachineInstrB
VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
// TODO: verify we have properly encoded deopt arguments
-
};
}
@@ -1947,9 +1946,11 @@ void MachineVerifier::verifyLiveRangeSeg
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
- // All predecessors must have a live-out value if this is not a
- // subregister liverange.
- if (!PVNI && LaneMask.none()) {
+ // All predecessors must have a live-out value. However for a phi
+ // instruction with subregister intervals
+ // only one of the subregisters (not necessarily the current one) needs to
+ // be defined.
+ if (!PVNI && (LaneMask.none() || !IsPHI) ) {
report("Register not marked live out of predecessor", *PI);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=305016&r1=305015&r2=305016&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Thu Jun 8 16:30:54 2017
@@ -738,7 +738,15 @@ void RegAllocPBQP::finalizeAlloc(Machine
if (PReg == 0) {
const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
- PReg = RC.getRawAllocationOrder(MF).front();
+ const ArrayRef<MCPhysReg> RawPRegOrder = RC.getRawAllocationOrder(MF);
+ for (unsigned CandidateReg : RawPRegOrder) {
+ if (!VRM.getRegInfo().isReserved(CandidateReg)) {
+ PReg = CandidateReg;
+ break;
+ }
+ }
+ assert(PReg &&
+ "No un-reserved physical registers in this register class");
}
VRM.assignVirt2Phys(LI.reg, PReg);
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=305016&r1=305015&r2=305016&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Jun 8 16:30:54 2017
@@ -72,6 +72,17 @@ void VirtRegMap::grow() {
Virt2SplitMap.resize(NumRegs);
}
+void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
+ TargetRegisterInfo::isPhysicalRegister(physReg));
+ assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
+ "attempt to assign physical register to already mapped "
+ "virtual register");
+ assert(!getRegInfo().isReserved(physReg) &&
+ "Attempt to map virtReg to a reserved physReg");
+ Virt2PhysMap[virtReg] = physReg;
+}
+
unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
unsigned Size = TRI->getSpillSize(*RC);
unsigned Align = TRI->getSpillAlignment(*RC);
Added: llvm/trunk/test/CodeGen/Mips/pbqp-reserved-physreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/pbqp-reserved-physreg.ll?rev=305016&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/pbqp-reserved-physreg.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/pbqp-reserved-physreg.ll Thu Jun 8 16:30:54 2017
@@ -0,0 +1,35 @@
+; RUN: llc -march=mips -regalloc=pbqp <%s > %t
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+
+; Function Attrs: nounwind
+define void @ham.928() local_unnamed_addr #0 align 2 {
+bb:
+ switch i32 undef, label %bb35 [
+ i32 1, label %bb18
+ i32 0, label %bb19
+ i32 3, label %bb20
+ i32 2, label %bb21
+ i32 4, label %bb17
+ ]
+
+bb17: ; preds = %bb
+ unreachable
+
+bb18: ; preds = %bb
+ unreachable
+
+bb19: ; preds = %bb
+ unreachable
+
+bb20: ; preds = %bb
+ unreachable
+
+bb21: ; preds = %bb
+ unreachable
+
+bb35: ; preds = %bb
+ unreachable
+}
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
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