[PATCH] D33298: [SROA] Fix APInt size when load/store have different address space
Yaxun Liu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 8 11:04:22 PDT 2017
yaxunl updated this revision to Diff 101944.
yaxunl retitled this revision from "[SROA] Fix adjusted pointer type and APInt size when load/store have different address space" to "[SROA] Fix APInt size when load/store have different address space".
yaxunl edited the summary of this revision.
yaxunl added a comment.
Rebased.
https://reviews.llvm.org/D33298
Files:
lib/Transforms/Scalar/SROA.cpp
test/Transforms/SROA/address-spaces.ll
Index: test/Transforms/SROA/address-spaces.ll
===================================================================
--- test/Transforms/SROA/address-spaces.ll
+++ test/Transforms/SROA/address-spaces.ll
@@ -100,4 +100,31 @@
%f2 = load float, float* %b.gep2
%ret = fadd float %f1, %f2
ret float %ret
+
+; Test load from and store to non-zero address space.
+define void @test_load_store_diff_addr_space([2 x float] addrspace(1)* %complex1, [2 x float] addrspace(1)* %complex2) {
+; CHECK-LABEL: @test_load_store_diff_addr_space
+; CHECK-NOT: alloca
+; CHECK: load i32, i32 addrspace(1)*
+; CHECK: load i32, i32 addrspace(1)*
+; CHECK: store i32 %{{.*}}, i32 addrspace(1)*
+; CHECK: store i32 %{{.*}}, i32 addrspace(1)*
+ %a = alloca i64
+ %a.cast = bitcast i64* %a to [2 x float]*
+ %a.gep1 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 0
+ %a.gep2 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 1
+ %complex1.gep = getelementptr [2 x float], [2 x float] addrspace(1)* %complex1, i32 0, i32 0
+ %p1 = bitcast float addrspace(1)* %complex1.gep to i64 addrspace(1)*
+ %v1 = load i64, i64 addrspace(1)* %p1
+ store i64 %v1, i64* %a
+ %f1 = load float, float* %a.gep1
+ %f2 = load float, float* %a.gep2
+ %sum = fadd float %f1, %f2
+ store float %sum, float* %a.gep1
+ store float %sum, float* %a.gep2
+ %v2 = load i64, i64* %a
+ %complex2.gep = getelementptr [2 x float], [2 x float] addrspace(1)* %complex2, i32 0, i32 0
+ %p2 = bitcast float addrspace(1)* %complex2.gep to i64 addrspace(1)*
+ store i64 %v2, i64 addrspace(1)* %p2
+ ret void
}
Index: lib/Transforms/Scalar/SROA.cpp
===================================================================
--- lib/Transforms/Scalar/SROA.cpp
+++ lib/Transforms/Scalar/SROA.cpp
@@ -3627,9 +3627,12 @@
PLoad->getType()->getPointerTo(SI->getPointerAddressSpace());
StoreInst *PStore = IRB.CreateAlignedStore(
- PLoad, getAdjustedPtr(IRB, DL, StoreBasePtr,
- APInt(DL.getPointerSizeInBits(), PartOffset),
- PartPtrTy, StoreBasePtr->getName() + "."),
+ PLoad,
+ getAdjustedPtr(
+ IRB, DL, StoreBasePtr,
+ APInt(DL.getPointerSizeInBits(SI->getPointerAddressSpace()),
+ PartOffset),
+ PartPtrTy, StoreBasePtr->getName() + "."),
getAdjustedAlignment(SI, PartOffset, DL), /*IsVolatile*/ false);
PStore->copyMetadata(*LI, LLVMContext::MD_mem_parallel_loop_access);
DEBUG(dbgs() << " +" << PartOffset << ":" << *PStore << "\n");
@@ -3708,19 +3711,24 @@
} else {
IRB.SetInsertPoint(LI);
PLoad = IRB.CreateAlignedLoad(
- getAdjustedPtr(IRB, DL, LoadBasePtr,
- APInt(DL.getPointerSizeInBits(), PartOffset),
- LoadPartPtrTy, LoadBasePtr->getName() + "."),
+ getAdjustedPtr(
+ IRB, DL, LoadBasePtr,
+ APInt(DL.getPointerSizeInBits(LI->getPointerAddressSpace()),
+ PartOffset),
+ LoadPartPtrTy, LoadBasePtr->getName() + "."),
getAdjustedAlignment(LI, PartOffset, DL), /*IsVolatile*/ false,
LI->getName());
}
// And store this partition.
IRB.SetInsertPoint(SI);
StoreInst *PStore = IRB.CreateAlignedStore(
- PLoad, getAdjustedPtr(IRB, DL, StoreBasePtr,
- APInt(DL.getPointerSizeInBits(), PartOffset),
- StorePartPtrTy, StoreBasePtr->getName() + "."),
+ PLoad,
+ getAdjustedPtr(
+ IRB, DL, StoreBasePtr,
+ APInt(DL.getPointerSizeInBits(SI->getPointerAddressSpace()),
+ PartOffset),
+ StorePartPtrTy, StoreBasePtr->getName() + "."),
getAdjustedAlignment(SI, PartOffset, DL), /*IsVolatile*/ false);
// Now build a new slice for the alloca.
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