[llvm] r304910 - AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal

Tom Stellard via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 7 06:54:51 PDT 2017


Author: tstellar
Date: Wed Jun  7 08:54:51 2017
New Revision: 304910

URL: http://llvm.org/viewvc/llvm-project?rev=304910&view=rev
Log:
AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33949

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=304910&r1=304909&r2=304910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Wed Jun  7 08:54:51 2017
@@ -56,6 +56,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
   setAction({G_LOAD, 1, P1}, Legal);
   setAction({G_LOAD, 1, P2}, Legal);
 
+  setAction({G_SELECT, S32}, Legal);
+  setAction({G_SELECT, 1, S1}, Legal);
+
   setAction({G_STORE, S32}, Legal);
   setAction({G_STORE, 1, P1}, Legal);
 

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir?rev=304910&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir Wed Jun  7 08:54:51 2017
@@ -0,0 +1,28 @@
+# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_select() { ret void }
+...
+
+---
+name:            test_select
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body: |
+  bb.0:
+    liveins: %vgpr0
+    %0(s32) = G_CONSTANT i32 0
+    %1(s32) = COPY %vgpr0
+
+    %2(s1) = G_ICMP intpred(ne), %0, %1
+    %3(s32) = G_CONSTANT i32 1
+    %4(s32) = G_CONSTANT i32 2
+    ; CHECK: %5(s32) = G_SELECT %2(s1), %3, %4
+    %5(s32) = G_SELECT %2, %3, %4
+
+...




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