[llvm] r304902 - [ARM] GlobalISel: Purge G_SEQUENCE
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 7 05:35:06 PDT 2017
Author: rovka
Date: Wed Jun 7 07:35:05 2017
New Revision: 304902
URL: http://llvm.org/viewvc/llvm-project?rev=304902&view=rev
Log:
[ARM] GlobalISel: Purge G_SEQUENCE
According to the commit message from r296921, G_MERGE_VALUES and
G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating
G_SEQUENCE in the ARM backend and remove the code dealing with it.
This boils down to the code breaking up double values for the soft float
calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of
G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR +
VMOVRRD and simplifies the code in the instruction selector.
There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but
that is part of the target-independent code for translating constant
structs. Therefore, it is beyond the scope of this commit.
Modified:
llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Wed Jun 7 07:35:05 2017
@@ -123,8 +123,7 @@ struct OutgoingValueHandler : public Cal
unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
MRI.createGenericVirtualRegister(LLT::scalar(32))};
- MIRBuilder.buildExtract(NewRegs[0], Arg.Reg, 0);
- MIRBuilder.buildExtract(NewRegs[1], Arg.Reg, 32);
+ MIRBuilder.buildUnmerge(NewRegs, Arg.Reg);
bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
if (!IsLittle)
@@ -340,7 +339,7 @@ struct IncomingValueHandler : public Cal
if (!IsLittle)
std::swap(NewRegs[0], NewRegs[1]);
- MIRBuilder.buildSequence(Arg.Reg, NewRegs, {0, 32});
+ MIRBuilder.buildMerge(Arg.Reg, NewRegs);
return 1;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Wed Jun 7 07:35:05 2017
@@ -127,34 +127,30 @@ static bool selectCopy(MachineInstr &I,
return true;
}
-static bool selectSequence(MachineInstrBuilder &MIB,
- const ARMBaseInstrInfo &TII,
- MachineRegisterInfo &MRI,
- const TargetRegisterInfo &TRI,
- const RegisterBankInfo &RBI) {
- assert(TII.getSubtarget().hasVFP2() && "Can't select sequence without VFP");
+static bool selectMergeValues(MachineInstrBuilder &MIB,
+ const ARMBaseInstrInfo &TII,
+ MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI,
+ const RegisterBankInfo &RBI) {
+ assert(TII.getSubtarget().hasVFP2() && "Can't select merge without VFP");
- // We only support G_SEQUENCE as a way to stick together two scalar GPRs
+ // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
// into one DPR.
unsigned VReg0 = MIB->getOperand(0).getReg();
(void)VReg0;
assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
- "Unsupported operand for G_SEQUENCE");
+ "Unsupported operand for G_MERGE_VALUES");
unsigned VReg1 = MIB->getOperand(1).getReg();
(void)VReg1;
assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
- "Unsupported operand for G_SEQUENCE");
- unsigned VReg2 = MIB->getOperand(3).getReg();
+ "Unsupported operand for G_MERGE_VALUES");
+ unsigned VReg2 = MIB->getOperand(2).getReg();
(void)VReg2;
assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
- "Unsupported operand for G_SEQUENCE");
-
- // Remove the operands corresponding to the offsets.
- MIB->RemoveOperand(4);
- MIB->RemoveOperand(2);
+ "Unsupported operand for G_MERGE_VALUES");
MIB->setDesc(TII.get(ARM::VMOVDRR));
MIB.add(predOps(ARMCC::AL));
@@ -162,30 +158,32 @@ static bool selectSequence(MachineInstrB
return true;
}
-static bool selectExtract(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
- MachineRegisterInfo &MRI,
- const TargetRegisterInfo &TRI,
- const RegisterBankInfo &RBI) {
- assert(TII.getSubtarget().hasVFP2() && "Can't select extract without VFP");
+static bool selectUnmergeValues(MachineInstrBuilder &MIB,
+ const ARMBaseInstrInfo &TII,
+ MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI,
+ const RegisterBankInfo &RBI) {
+ assert(TII.getSubtarget().hasVFP2() && "Can't select unmerge without VFP");
- // We only support G_EXTRACT as a way to break up one DPR into two GPRs.
+ // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
+ // GPRs.
unsigned VReg0 = MIB->getOperand(0).getReg();
(void)VReg0;
assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
- "Unsupported operand for G_EXTRACT");
+ "Unsupported operand for G_UNMERGE_VALUES");
unsigned VReg1 = MIB->getOperand(1).getReg();
(void)VReg1;
- assert(MRI.getType(VReg1).getSizeInBits() == 64 &&
- RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::FPRRegBankID &&
- "Unsupported operand for G_EXTRACT");
- assert(MIB->getOperand(2).getImm() % 32 == 0 &&
- "Unsupported operand for G_EXTRACT");
-
- // Remove the operands corresponding to the offsets.
- MIB->getOperand(2).setImm(MIB->getOperand(2).getImm() / 32);
+ assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
+ RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
+ "Unsupported operand for G_UNMERGE_VALUES");
+ unsigned VReg2 = MIB->getOperand(2).getReg();
+ (void)VReg2;
+ assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
+ RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
+ "Unsupported operand for G_UNMERGE_VALUES");
- MIB->setDesc(TII.get(ARM::VGETLNi32));
+ MIB->setDesc(TII.get(ARM::VMOVRRD));
MIB.add(predOps(ARMCC::AL));
return true;
@@ -407,13 +405,13 @@ bool ARMInstructionSelector::select(Mach
MIB.addImm(0).add(predOps(ARMCC::AL));
break;
}
- case G_SEQUENCE: {
- if (!selectSequence(MIB, TII, MRI, TRI, RBI))
+ case G_MERGE_VALUES: {
+ if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
return false;
break;
}
- case G_EXTRACT: {
- if (!selectExtract(MIB, TII, MRI, TRI, RBI))
+ case G_UNMERGE_VALUES: {
+ if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
return false;
break;
}
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Wed Jun 7 07:35:05 2017
@@ -255,30 +255,32 @@ ARMRegisterBankInfo::getInstrMapping(con
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
break;
- case G_SEQUENCE: {
- // We only support G_SEQUENCE for creating a double precision floating point
- // value out of two GPRs.
+ case G_MERGE_VALUES: {
+ // We only support G_MERGE_VALUES for creating a double precision floating
+ // point value out of two GPRs.
LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
- LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
+ LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
Ty2.getSizeInBits() != 32)
return getInvalidInstructionMapping();
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
- &ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
- &ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
+ &ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::GPR3OpsIdx]});
break;
}
- case G_EXTRACT: {
- // We only support G_EXTRACT for splitting a double precision floating point
- // value into two GPRs.
+ case G_UNMERGE_VALUES: {
+ // We only support G_UNMERGE_VALUES for splitting a double precision
+ // floating point value into two GPRs.
LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
- if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 64 ||
- MI.getOperand(2).getImm() % 32 != 0)
+ LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
+ if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
+ Ty2.getSizeInBits() != 64)
return getInvalidInstructionMapping();
- OperandsMapping = getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
- &ARM::ValueMappings[ARM::DPR3OpsIdx],
- nullptr, nullptr});
+ OperandsMapping =
+ getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::DPR3OpsIdx]});
break;
}
default:
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Wed Jun 7 07:35:05 2017
@@ -1127,13 +1127,11 @@ body: |
%1(s32) = COPY %r3
; CHECK: [[IN2:%[0-9]+]] = COPY %r3
- %2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 1
+ %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; CHECK: %[[DREG]] = VMOVDRR [[IN1]], [[IN2]]
- %3(s32) = G_EXTRACT %2(s64), 0
- %4(s32) = G_EXTRACT %2(s64), 32
- ; CHECK: [[OUT1:%[0-9]+]] = VGETLNi32 %[[DREG]], 0
- ; CHECK: [[OUT2:%[0-9]+]] = VGETLNi32 %[[DREG]], 1
+ %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
+ ; CHECK: [[OUT1:%[0-9]+]], [[OUT2:%[0-9]+]] = VMOVRRD %[[DREG]]
%r0 = COPY %3
; CHECK: %r0 = COPY [[OUT1]]
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll Wed Jun 7 07:35:05 2017
@@ -329,15 +329,13 @@ define arm_aapcscc double @test_double_a
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[VREGP1LO:%[0-9]+]](s32) = COPY %r2
; CHECK-DAG: [[VREGP1HI:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[VREGP1:%[0-9]+]](s64) = G_SEQUENCE [[VREGP1LO]](s32), 0, [[VREGP1HI]](s32), 32
-; BIG: [[VREGP1:%[0-9]+]](s64) = G_SEQUENCE [[VREGP1HI]](s32), 0, [[VREGP1LO]](s32), 32
+; LITTLE: [[VREGP1:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
+; BIG: [[VREGP1:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]](s64) = G_LOAD [[FIP5]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGP5]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
-; BIG: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; BIG: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
+; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -376,15 +374,13 @@ define arm_aapcscc double @test_double_g
; CHECK: liveins: %r0, %r2, %r3
; CHECK-DAG: [[VREGP0LO:%[0-9]+]](s32) = COPY %r2
; CHECK-DAG: [[VREGP0HI:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0LO]](s32), 0, [[VREGP0HI]](s32), 32
-; BIG: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0HI]](s32), 0, [[VREGP0LO]](s32), 32
+; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
+; BIG: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
-; BIG: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; BIG: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
+; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -401,15 +397,13 @@ define arm_aapcscc double @test_double_g
; CHECK: liveins: %r0, %r1, %r2
; CHECK-DAG: [[VREGP0LO:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[VREGP0HI:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0LO]](s32), 0, [[VREGP0HI]](s32), 32
-; BIG: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0HI]](s32), 0, [[VREGP0LO]](s32), 32
+; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
+; BIG: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
-; BIG: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0
-; BIG: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32
+; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -568,13 +562,12 @@ define arm_aapcscc double @test_call_aap
; CHECK-LABEL: name: test_call_aapcs_fp_params
; CHECK-DAG: [[A1:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[A2:%[0-9]+]](s32) = COPY %r1
-; LITTLE-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A1]](s32), 0, [[A2]](s32), 32
-; BIG-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A2]](s32), 0, [[A1]](s32), 32
+; LITTLE-DAG: [[AVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
+; BIG-DAG: [[AVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r2
; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp
; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: [[A1:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 0
-; CHECK-DAG: [[A2:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 32
+; CHECK-DAG: [[A1:%[0-9]+]](s32), [[A2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[AVREG]](s64)
; LITTLE-DAG: %r2 = COPY [[A1]]
; LITTLE-DAG: %r3 = COPY [[A2]]
; BIG-DAG: %r2 = COPY [[A2]]
@@ -590,11 +583,10 @@ define arm_aapcscc double @test_call_aap
; CHECK: BLX @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[RVREG:%[0-9]+]](s64) = G_SEQUENCE [[R1]](s32), 0, [[R2]](s32), 32
-; BIG: [[RVREG:%[0-9]+]](s64) = G_SEQUENCE [[R2]](s32), 0, [[R1]](s32), 32
+; LITTLE: [[RVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
+; BIG: [[RVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RVREG]](s64), 0
-; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[RVREG]](s64), 32
+; CHECK: [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RVREG]](s64)
; LITTLE-DAG: %r0 = COPY [[R1]]
; LITTLE-DAG: %r1 = COPY [[R2]]
; BIG-DAG: %r0 = COPY [[R2]]
@@ -761,12 +753,12 @@ define arm_aapcscc [2 x float] @test_fp_
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[ARR0_0:%[0-9]+]](s32) = COPY %r0
; CHECK: [[ARR0_1:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_0]](s32), 0, [[ARR0_1]](s32), 32
-; BIG: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_1]](s32), 0, [[ARR0_0]](s32), 32
+; LITTLE: [[ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
+; BIG: [[ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]](s32) = COPY %r2
; CHECK: [[ARR1_1:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[ARR1:%[0-9]+]](s64) = G_SEQUENCE [[ARR1_0]](s32), 0, [[ARR1_1]](s32), 32
-; BIG: [[ARR1:%[0-9]+]](s64) = G_SEQUENCE [[ARR1_1]](s32), 0, [[ARR1_0]](s32), 32
+; LITTLE: [[ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
+; BIG: [[ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]](s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR_MERGED_0:%[0-9]+]](s192) = IMPLICIT_DEF
@@ -778,14 +770,12 @@ define arm_aapcscc [2 x float] @test_fp_
; CHECK: [[ARR0:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 0
; CHECK: [[ARR1:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 64
; CHECK: [[ARR2:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 128
-; CHECK: [[ARR0_0:%[0-9]+]](s32) = G_EXTRACT [[ARR0]](s64), 0
-; CHECK: [[ARR0_1:%[0-9]+]](s32) = G_EXTRACT [[ARR0]](s64), 32
+; CHECK: [[ARR0_0:%[0-9]+]](s32), [[ARR0_1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARR0]](s64)
; LITTLE: %r0 = COPY [[ARR0_0]](s32)
; LITTLE: %r1 = COPY [[ARR0_1]](s32)
; BIG: %r0 = COPY [[ARR0_1]](s32)
; BIG: %r1 = COPY [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]](s32) = G_EXTRACT [[ARR1]](s64), 0
-; CHECK: [[ARR1_1:%[0-9]+]](s32) = G_EXTRACT [[ARR1]](s64), 32
+; CHECK: [[ARR1_0:%[0-9]+]](s32), [[ARR1_1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARR1]](s64)
; LITTLE: %r2 = COPY [[ARR1_0]](s32)
; LITTLE: %r3 = COPY [[ARR1_1]](s32)
; BIG: %r2 = COPY [[ARR1_1]](s32)
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll Wed Jun 7 07:35:05 2017
@@ -353,8 +353,7 @@ define arm_aapcscc double @test_double_s
; CHECK-DAG: vmov [[F0:d[0-9]+]], r0, r1
; CHECK-DAG: vmov [[F1:d[0-9]+]], r2, r3
; CHECK: vadd.f64 [[FV:d[0-9]+]], [[F0]], [[F1]]
-; CHECK: vmov.32 r0, [[FV]][0]
-; CHECK: vmov.32 r1, [[FV]][1]
+; CHECK: vmov r0, r1, [[FV]]
; CHECK: bx lr
entry:
%v = fadd double %f0, %f1
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Wed Jun 7 07:35:05 2017
@@ -82,10 +82,10 @@ body: |
%1(s32) = COPY %r1
%2(s32) = COPY %r2
%3(s32) = COPY %r3
- ; HARD-DAG: [[X:%[0-9]+]](s64) = G_SEQUENCE [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_SEQUENCE [[Y0]]
- %4(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
- %5(s64) = G_SEQUENCE %2(s32), 0, %3(s32), 32
+ ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK: ADJCALLSTACKDOWN
; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
@@ -97,8 +97,7 @@ body: |
; HARD: BLX $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: ADJCALLSTACKUP
%6(s64) = G_FREM %4, %5
- %7(s32) = G_EXTRACT %6(s64), 0
- %8(s32) = G_EXTRACT %6(s64), 32
+ %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32)
%r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1
@@ -174,10 +173,10 @@ body: |
%1(s32) = COPY %r1
%2(s32) = COPY %r2
%3(s32) = COPY %r3
- ; HARD-DAG: [[X:%[0-9]+]](s64) = G_SEQUENCE [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_SEQUENCE [[Y0]]
- %4(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
- %5(s64) = G_SEQUENCE %2(s32), 0, %3(s32), 32
+ ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK: ADJCALLSTACKDOWN
; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
@@ -189,8 +188,7 @@ body: |
; HARD: BLX $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: ADJCALLSTACKUP
%6(s64) = G_FPOW %4, %5
- %7(s32) = G_EXTRACT %6(s64), 0
- %8(s32) = G_EXTRACT %6(s64), 32
+ %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32)
%r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1
@@ -258,10 +256,10 @@ body: |
%1(s32) = COPY %r1
%2(s32) = COPY %r2
%3(s32) = COPY %r3
- ; HARD-DAG: [[X:%[0-9]+]](s64) = G_SEQUENCE [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_SEQUENCE [[Y0]]
- %4(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
- %5(s64) = G_SEQUENCE %2(s32), 0, %3(s32), 32
+ ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; HARD: [[R:%[0-9]+]](s64) = G_FADD [[X]], [[Y]]
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
@@ -272,10 +270,8 @@ body: |
; SOFT-DEFAULT: BLX $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; SOFT: ADJCALLSTACKUP
%6(s64) = G_FADD %4, %5
- ; HARD-DAG: G_EXTRACT [[R]](s64), 0
- ; HARD-DAG: G_EXTRACT [[R]](s64), 32
- %7(s32) = G_EXTRACT %6(s64), 0
- %8(s32) = G_EXTRACT %6(s64), 32
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+ %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32)
%r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=304902&r1=304901&r2=304902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Wed Jun 7 07:35:05 2017
@@ -787,9 +787,8 @@ body: |
%0(s32) = COPY %r0
%1(s32) = COPY %r1
- %2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
- %3(s32) = G_EXTRACT %2(s64), 0
- %4(s32) = G_EXTRACT %2(s64), 32
+ %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
%r0 = COPY %3(s32)
%r1 = COPY %4(s32)
BX_RET 14, _, implicit %r0, implicit %r1
More information about the llvm-commits
mailing list