[PATCH] D33954: [ARM] GlobalISel: Constrain callee register on indirect calls

[Alexey Bataev via Phabricator via llvm-commits]

ABataev created this revision.
Herald added subscribers: kristof.beyls, igorb, rovka, mzolotukhin, aemerson.

When lowering calls, we generate instructions with machine opcodes
rather than generic ones. Therefore, we need to constrain the register
classes of the operands.

Also enable the machine verifier on the arm-irtranslator.ll test, since
that would've caught this issue.

Fixes (part of) PR32146.

[SLP] Fix for PR32164: Improve vectorization of  reverse order of extract operations.

Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation.


https://reviews.llvm.org/D33954

Files:
  lib/Transforms/Vectorize/SLPVectorizer.cpp
  test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll

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