[PATCH] D33836: [AArch64] Enable FeatureFuseAES for the generic processor model.

[silviu.baranga@arm.com via Phabricator via llvm-commits]

sbaranga added a comment.

We already have the IR in misched-fusion-aes.ll that can be used for microbenchmarks (just call the functions in a loop)? I think that should be theoretically enough for an evaluation.

Cheers,
Silviu


https://reviews.llvm.org/D33836