[llvm] r304801 - [mips] Add madd4 subtarget feature
Petar Jovanovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 6 08:33:01 PDT 2017
Author: petarj
Date: Tue Jun 6 10:33:01 2017
New Revision: 304801
URL: http://llvm.org/viewvc/llvm-project?rev=304801&view=rev
Log:
[mips] Add madd4 subtarget feature
Addition of a feature and a predicate used to control generation of madd.fmt
and similar instructions.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D33400
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/test/CodeGen/Mips/fmadd1.ll
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Tue Jun 6 10:33:01 2017
@@ -185,6 +185,9 @@ def FeatureUseTCCInDIV : SubtargetFeatur
"UseTCCInDIV", "false",
"Force the assembler to use trapping">;
+def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
+ "Disable 4-operand madd.fmt and related instructions">;
+
//===----------------------------------------------------------------------===//
// Mips processors supported.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Jun 6 10:33:01 2017
@@ -557,11 +557,11 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
- MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
+ MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
- MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
+ MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
-let AdditionalPredicates = [NoNaNsFPMath] in {
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
@@ -569,11 +569,11 @@ let AdditionalPredicates = [NoNaNsFPMath
}
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
- MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
+ MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
- MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
+ MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
-let AdditionalPredicates = [NoNaNsFPMath] in {
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
@@ -582,12 +582,12 @@ let AdditionalPredicates = [NoNaNsFPMath
let DecoderNamespace = "Mips64" in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
- MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
+ MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
- MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
+ MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
}
-let AdditionalPredicates = [NoNaNsFPMath],
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
DecoderNamespace = "Mips64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jun 6 10:33:01 2017
@@ -238,6 +238,8 @@ def HasEVA : Predicate<"Subtarg
AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
+def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
+ AssemblerPredicate<"!FeatureMadd4">;
//===----------------------------------------------------------------------===//
@@ -390,6 +392,10 @@ class ASE_NOT_DSP {
list<Predicate> InsnPredicates = [NotDSP];
}
+class MADD4 {
+ list<Predicate> AdditionalPredicates = [HasMadd4];
+}
+
//===----------------------------------------------------------------------===//
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Jun 6 10:33:01 2017
@@ -70,7 +70,7 @@ MipsSubtarget::MipsSubtarget(const Tripl
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
- HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
+ HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)),
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Jun 6 10:33:01 2017
@@ -144,6 +144,10 @@ class MipsSubtarget : public MipsGenSubt
// HasEVA -- supports EVA ASE.
bool HasEVA;
+
+ // nomadd4 - disables generation of 4-operand madd.s, madd.d and
+ // related instructions.
+ bool DisableMadd4;
InstrItineraryData InstrItins;
@@ -253,6 +257,7 @@ public:
bool hasDSPR2() const { return HasDSPR2; }
bool hasDSPR3() const { return HasDSPR3; }
bool hasMSA() const { return HasMSA; }
+ bool disableMadd4() const { return DisableMadd4; }
bool hasEVA() const { return HasEVA; }
bool useSmallSection() const { return UseSmallSection; }
Modified: llvm/trunk/test/CodeGen/Mips/fmadd1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fmadd1.ll?rev=304801&r1=304800&r2=304801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fmadd1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fmadd1.ll Tue Jun 6 10:33:01 2017
@@ -5,52 +5,63 @@
; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
; available when -enable-no-nans-fp-math is given.
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32,32-NONAN
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6,32R6-NONAN
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NONAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6,64R6-NONAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
+
+; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
+; when +nomadd attribute is specified.
+; Output for mips32 and mips64r6 reused since aforementioned instructions are
+; not generated in those cases.
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
entry:
; ALL-LABEL: FOO0float:
-; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
-
-; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2: add.s $f0, $[[T1]], $[[T2]]
-
-; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
-
-; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
-
-; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2: add.s $f0, $[[T0]], $[[T1]]
-
-; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
-; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
-; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
+; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
+
+; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2: add.s $f0, $[[T1]], $[[T2]]
+
+; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
+
+; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
+
+; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2: add.s $f0, $[[T0]], $[[T1]]
+
+; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
+; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b
%add = fadd float %mul, %c
@@ -62,35 +73,35 @@ define float @FOO1float(float %a, float
entry:
; ALL-LABEL: FOO1float:
-; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
-
-; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2: add.s $f0, $[[T1]], $[[T2]]
-
-; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
-
-; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
-
-; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2: add.s $f0, $[[T0]], $[[T1]]
-
-; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
-; 64R6-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
-; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
+; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
+
+; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2: add.s $f0, $[[T1]], $[[T2]]
+
+; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
+
+; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
+
+; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2: add.s $f0, $[[T0]], $[[T1]]
+
+; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
+; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
@@ -102,42 +113,42 @@ define float @FOO2float(float %a, float
entry:
; ALL-LABEL: FOO2float:
-; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
-
-; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
-
-; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
-
-; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
-
-; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
-
-; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
-
-; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
-
-; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
-
-; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
+; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
+
+; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
+
+; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
+
+; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
+
+; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
+
+; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
+
+; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
+
+; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
+
+; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b
%add = fadd float %mul, %c
@@ -149,34 +160,34 @@ define float @FOO3float(float %a, float
entry:
; ALL-LABEL: FOO3float:
-; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
-; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
-
-; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
-
-; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
-; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
-
-; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
-
-; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
-
-; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
-
-; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
+; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
+; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
+
+; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
+
+; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
+; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
+
+; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
+
+; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
+
+; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
+
+; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
@@ -188,36 +199,36 @@ define double @FOO10double(double %a, do
entry:
; ALL-LABEL: FOO10double:
-; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
-
-; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2: mthc1 $zero, $[[T2]]
-; 32R2: add.d $f0, $[[T1]], $[[T2]]
-
-; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
-
-; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
-
-; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2: add.d $f0, $[[T0]], $[[T1]]
-
-; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
+; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
+
+; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2: mthc1 $zero, $[[T2]]
+; 32R2: add.d $f0, $[[T1]], $[[T2]]
+
+; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
+
+; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
+
+; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2: add.d $f0, $[[T0]], $[[T1]]
+
+; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b
%add = fadd double %mul, %c
@@ -229,36 +240,36 @@ define double @FOO11double(double %a, do
entry:
; ALL-LABEL: FOO11double:
-; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
-
-; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2: mthc1 $zero, $[[T2]]
-; 32R2: add.d $f0, $[[T1]], $[[T2]]
-
-; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
-
-; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
-
-; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2: add.d $f0, $[[T0]], $[[T1]]
-
-; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
+; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
+
+; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2: mthc1 $zero, $[[T2]]
+; 32R2: add.d $f0, $[[T1]], $[[T2]]
+
+; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
+
+; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
+
+; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2: add.d $f0, $[[T0]], $[[T1]]
+
+; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b
%sub = fsub double %mul, %c
@@ -270,43 +281,43 @@ define double @FOO12double(double %a, do
entry:
; ALL-LABEL: FOO12double:
-; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
-
-; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
-
-; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2-NAN: mthc1 $zero, $[[T2]]
-; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
-
-; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
-
-; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
-
-; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
-
-; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
-
-; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
-
-; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
+; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
+
+; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
+
+; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN: mthc1 $zero, $[[T2]]
+; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
+
+; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
+
+; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
+
+; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
+
+; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
+
+; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
+
+; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b
%add = fadd double %mul, %c
@@ -318,43 +329,43 @@ define double @FOO13double(double %a, do
entry:
; ALL-LABEL: FOO13double:
-; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
-
-; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
-
-; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R2-NAN: mthc1 $zero, $[[T2]]
-; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
-
-; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
-; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
-; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
-; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
-
-; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
-
-; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
-
-; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
-
-; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
-; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
-; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
-
-; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
-; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
-; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
+; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
+
+; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
+
+; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
+; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN: mthc1 $zero, $[[T2]]
+; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
+
+; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
+; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
+; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
+; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
+
+; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
+
+; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
+
+; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
+
+; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
+
+; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
+; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
+; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
+; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b
%sub = fsub double %mul, %c
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