[PATCH] D33203: Add scheduler classes to integer/float horizontal operations

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added inline comments.


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Comment at: lib/Target/X86/X86SchedHaswell.td:1530
+// v <- v,v.
+def : InstRW<[WritePHAdd], (instregex "MMX_PHADD(W?)rr64",
                                "MMX_PHADDSWrr64",
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Please see the accurate modeling I added for these instrs in https://reviews.llvm.org/D33897



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Comment at: lib/Target/X86/X86SchedHaswell.td:1538
 // v <- v,m.
-def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
-  let Latency = 6;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1, 2, 1];
-}
-def : InstRW<[WritePHADDSUBm, ReadAfterLd],
+def : InstRW<[WritePHAddLd, ReadAfterLd],
                               (instregex "MMX_PHADD(W?)rm64",
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Please see the accurate modeling I added for these instrs in https://reviews.llvm.org/D33897



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Comment at: lib/Target/X86/X86SchedHaswell.td:1901
 // x,x / v,v,v.
-def WriteHADDSUBPr : SchedWriteRes<[HWPort1, HWPort5]> {
-  let Latency = 5;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1, 2];
-}
-def : InstRW<[WriteHADDSUBPr], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rr")>;
-
+def : InstRW<[WriteHAdd], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rr")>;
 // x,m / v,v,m.
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Please see the accurate modeling I added for these instrs in https://reviews.llvm.org/D33897



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Comment at: lib/Target/X86/X86SchedHaswell.td:1903
 // x,m / v,v,m.
-def WriteHADDSUBPm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
-  let Latency = 9;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1, 2, 1];
-}
-def : InstRW<[WriteHADDSUBPm], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rm")>;
+def : InstRW<[WriteHAddLd], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rm")>;
 
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Please see the accurate modeling I added for these instrs in https://reviews.llvm.org/D33897



https://reviews.llvm.org/D33203