[PATCH] D31710: [AMDGPU] Fix for issue in alloca to vector promotion pass

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp:401
+  case Instruction::Load: {
+    // Currently only handle the case where the Pointer Operand is a GEP so check for that
+    LoadInst *LI = cast<LoadInst>(Inst);
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Incomplete comment


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Comment at: lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp:409-410
   case Instruction::Store: {
-    // Must be the stored pointer operand, not a stored value.
+    // Must be the stored pointer operand, not a stored value, plus
+    // since it should be canonical form, the User should be a GEP
     StoreInst *SI = cast<StoreInst>(Inst);
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Same comment leftover


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Comment at: test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll:40
+; OPT-LABEL: @promote_store_aggr(
+
+%Block2 = type { i32, [2 x float] }
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These tests are all missing check lines


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Comment at: test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll:47
+  %f1 = alloca [2 x float]
+  %tmp = getelementptr %Block2, %Block2 addrspace(7)* @block2, i32 0, i32 0
+  %tmp1 = load i32, i32 addrspace(7)* %tmp
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What are address spaces 6 and 7? We can't codegen these, and it is somewhat preferable to be able to codegen any IR tests (although there are some exceptions)


https://reviews.llvm.org/D31710