[PATCH] D33864: [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve coalescing/combine opportunities

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL304688: [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve… (authored by RKSimon).

Changed prior to commit:
  https://reviews.llvm.org/D33864?vs=101317&id=101367#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D33864

Files:
  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
  llvm/trunk/test/CodeGen/X86/build-vector-128.ll
  llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/trunk/test/CodeGen/X86/clear_upper_vector_element_bits.ll
  llvm/trunk/test/CodeGen/X86/haddsub-2.ll
  llvm/trunk/test/CodeGen/X86/haddsub-undef.ll
  llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
  llvm/trunk/test/CodeGen/X86/select.ll
  llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
  llvm/trunk/test/CodeGen/X86/sse1.ll
  llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
  llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll
  llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll
  llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll
  llvm/trunk/test/CodeGen/X86/vec_set.ll
  llvm/trunk/test/CodeGen/X86/vector-rem.ll
  llvm/trunk/test/CodeGen/X86/vector-sext.ll
  llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-128.ll
  llvm/trunk/test/CodeGen/X86/vshift-1.ll
  llvm/trunk/test/CodeGen/X86/vshift-2.ll

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