[PATCH] D33188: [X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant shift left+right instructions).

[Zvi Rackover via Phabricator via llvm-commits]

zvi added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:5069
+// destination and accepts mask.
+static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
+  switch (Opcode) {
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If think you should check here for AND


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Comment at: lib/Target/X86/X86ISelLowering.cpp:5106
 
+  // If this node promotes - by concatenating zeroes - the type of the result
+  // of a node with instruction that zeroes all upper (irrelevant) bits of the
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promotes -> widens ?


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Comment at: lib/Target/X86/X86ISelLowering.cpp:5109
+  // output register, mark this nodes as legal to enable replacing them with
+  // the v8i1 version of the previous instruction duting instruction selection.
+  SDValue Inserted = Op.getOperand(1);
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*during


https://reviews.llvm.org/D33188