[PATCH] D33860: [AMDGPU] Untangle SDWA pass from SIShrinkInstructions

[Sam Kolton via Phabricator via llvm-commits]

SamWot added a comment.

This is good change. I wanted to propose it myself:)



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Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:261
     Mods |= Abs ? SISrcMods::ABS : 0;
-    Mods |= Neg ? SISrcMods::NEG : 0;
+    Mods ^= Neg ? SISrcMods::NEG : 0;
   } else if (Sext) {
----------------
Why do you use XOR here?


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Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:617
+  int Opc32 = AMDGPU::getVOPe32(Opc);
+  if (Opc32 != -1 && AMDGPU::getSDWAOp(Opc32) != -1)
+    return true;
----------------
This check isn't strong enough. E.g. VOP3 (e64) instructions allow OMod that is not allowed in SDWA on VI.
Another problem is SDST operand.  E.g. this is a valid instruction: v_add_i32_e64 v0, s[0:1], v1, v2. It writes carry-out into s[0:1] instead of VCC.
Same problem can be with VOPC version of VOP3.
You should either check for SDST operand or add special legalizer for it.


Repository:
  rL LLVM

https://reviews.llvm.org/D33860