[PATCH] D33596: [globalisel][tablegen] Add support for EXTRACT_SUBREG.

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

Could you re-upload the patch without the diffs from https://reviews.llvm.org/D33590?



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Comment at: test/CodeGen/AArch64/GlobalISel/select-trunc.mir:19
+# CHECK-NEXT:  - { id: 0, class: gpr64all }
+# CHECK-NEXT:  - { id: 1, class: gpr32sp }
 registers:
----------------
Do you know why we end up with 'all' in one case and 'sp' in the other?
I would have expected to both have 'all' or 'sp'.


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Comment at: utils/TableGen/CodeGenRegisters.h:368
+    /// SubRegClass and the largest subregister class that contains those
+    /// subregisters without (as far as possible) also containing additional registers.
+    ///
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The "as far as possible" part doesn't sound right. I thought tablegen was generating the missing register classes for that. 


https://reviews.llvm.org/D33596