[PATCH] D33836: [AArch64] Enable FeatureFuseAES for the generic processor model.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

Since it follows the precedent in GCC, I am fine with it.  I suspect that targets that do not support this, whether in order or out of order, would perform the same.  Can you share any data, @fhahn?


https://reviews.llvm.org/D33836