[PATCH] D33836: [AArch64] Enable FeatureFuseAES for the generic processor model.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
Herald added a subscriber: aemerson.

Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back
gives a double digit speedup on benchmarks using those instructions on
Cortex-A processors. In GCC, this optimization is part of the generic
processor model as well.

This change should not have a major performance impact on processors
that do not optimize AES instruction pairs, although I only had access
to Cortex-A processors for benchmarking.


https://reviews.llvm.org/D33836

Files:
  lib/Target/AArch64/AArch64.td
  test/CodeGen/AArch64/misched-fusion-aes.ll


Index: test/CodeGen/AArch64/misched-fusion-aes.ll
===================================================================
--- test/CodeGen/AArch64/misched-fusion-aes.ll
+++ test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -1,3 +1,4 @@
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
Index: lib/Target/AArch64/AArch64.td
===================================================================
--- lib/Target/AArch64/AArch64.td
+++ lib/Target/AArch64/AArch64.td
@@ -362,6 +362,7 @@
 
 def : ProcessorModel<"generic", NoSchedModel, [
                      FeatureFPARMv8,
+                     FeatureFuseAES,
                      FeatureNEON,
                      FeaturePerfMon,
                      FeaturePostRAScheduler


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