[llvm] r304547 - Regenerate and-sink.ll test results. NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 2 07:02:46 PDT 2017
Author: deadalnix
Date: Fri Jun 2 09:02:46 2017
New Revision: 304547
URL: http://llvm.org/viewvc/llvm-project?rev=304547&view=rev
Log:
Regenerate and-sink.ll test results. NFC
Modified:
llvm/trunk/test/CodeGen/X86/and-sink.ll
Modified: llvm/trunk/test/CodeGen/X86/and-sink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/and-sink.ll?rev=304547&r1=304546&r2=304547&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/and-sink.ll (original)
+++ llvm/trunk/test/CodeGen/X86/and-sink.ll Fri Jun 2 09:02:46 2017
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i686-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
@@ -8,12 +9,20 @@
; Test that 'and' is sunk into bb0.
define i32 @and_sink1(i32 %a, i1 %c) {
; CHECK-LABEL: and_sink1:
-; CHECK: testb $1,
-; CHECK: je
-; CHECK-NOT: andl $4,
-; CHECK: movl $0, A
-; CHECK: testb $4,
-; CHECK: jne
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
+; CHECK-NEXT: je .LBB0_3
+; CHECK-NEXT: # BB#1: # %bb0
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl $0, A
+; CHECK-NEXT: testb $4, %al
+; CHECK-NEXT: jne .LBB0_3
+; CHECK-NEXT: # BB#2: # %bb1
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB0_3: # %bb2
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retl
; CHECK-CGP-LABEL: @and_sink1(
; CHECK-CGP-NOT: and i32
@@ -37,16 +46,30 @@ bb2:
; Test that both 'and' and cmp get sunk to bb1.
define i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
; CHECK-LABEL: and_sink2:
-; CHECK: movl $0, A
-; CHECK: testb $1,
-; CHECK: je
-; CHECK-NOT: andl $4,
-; CHECK: movl $0, B
-; CHECK: testb $1,
-; CHECK: je
-; CHECK: movl $0, C
-; CHECK: testb $4,
-; CHECK: jne
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $0, A
+; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
+; CHECK-NEXT: je .LBB1_5
+; CHECK-NEXT: # BB#1: # %bb0.preheader
+; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB1_2: # %bb0
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movl $0, B
+; CHECK-NEXT: testb $1, %al
+; CHECK-NEXT: je .LBB1_5
+; CHECK-NEXT: # BB#3: # %bb1
+; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: movl $0, C
+; CHECK-NEXT: testb $4, %cl
+; CHECK-NEXT: jne .LBB1_2
+; CHECK-NEXT: # BB#4: # %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB1_5: # %bb3
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retl
; CHECK-CGP-LABEL: @and_sink2(
; CHECK-CGP-NOT: and i32
@@ -77,12 +100,21 @@ bb3:
; Test that CodeGenPrepare doesn't get stuck in a loop sinking and hoisting a masked load.
define i32 @and_sink3(i1 %c, i32* %p) {
; CHECK-LABEL: and_sink3:
-; CHECK: testb $1,
-; CHECK: je
-; CHECK: movzbl
-; CHECK-DAG: movl $0, A
-; CHECK-DAG: testl %
-; CHECK: je
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
+; CHECK-NEXT: je .LBB2_3
+; CHECK-NEXT: # BB#1: # %bb0
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movzbl (%eax), %eax
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: movl $0, A
+; CHECK-NEXT: je .LBB2_2
+; CHECK-NEXT: .LBB2_3: # %bb2
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB2_2: # %bb1
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retl
; CHECK-CGP-LABEL: @and_sink3(
; CHECK-CGP: load i32
@@ -106,15 +138,26 @@ bb2:
; Test that CodeGenPrepare sinks/duplicates non-immediate 'and'.
define i32 @and_sink4(i32 %a, i32 %b, i1 %c) {
; CHECK-LABEL: and_sink4:
-; CHECK: testb $1,
-; CHECK: je
-; CHECK-NOT: andl
-; CHECK-DAG: movl $0, A
-; CHECK-DAG: testl [[REG1:%[a-z0-9]+]], [[REG2:%[a-z0-9]+]]
-; CHECK: jne
-; CHECK-DAG: movl {{%[a-z0-9]+}}, B
-; CHECK-DAG: testl [[REG1]], [[REG2]]
-; CHECK: je
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
+; CHECK-NEXT: je .LBB3_4
+; CHECK-NEXT: # BB#1: # %bb0
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: testl %eax, %ecx
+; CHECK-NEXT: movl $0, A
+; CHECK-NEXT: jne .LBB3_4
+; CHECK-NEXT: # BB#2: # %bb1
+; CHECK-NEXT: leal (%ecx,%eax), %edx
+; CHECK-NEXT: testl %eax, %ecx
+; CHECK-NEXT: movl %edx, B
+; CHECK-NEXT: je .LBB3_3
+; CHECK-NEXT: .LBB3_4: # %bb3
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB3_3: # %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retl
; CHECK-CGP-LABEL: @and_sink4(
; CHECK-CGP-NOT: and i32
@@ -146,14 +189,26 @@ bb3:
; when it would increase register pressure.
define i32 @and_sink5(i32 %a, i32 %b, i32 %a2, i32 %b2, i1 %c) {
; CHECK-LABEL: and_sink5:
-; CHECK: testb $1,
-; CHECK: je
-; CHECK-DAG: andl {{[0-9]+\(%[a-z0-9]+\)}}, [[REG:%[a-z0-9]+]]
-; CHECK-DAG: movl $0, A
-; CHECK: jne
-; CHECK-DAG: movl {{%[a-z0-9]+}}, B
-; CHECK-DAG: testl [[REG]], [[REG]]
-; CHECK: je
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
+; CHECK-NEXT: je .LBB4_4
+; CHECK-NEXT: # BB#1: # %bb0
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl $0, A
+; CHECK-NEXT: jne .LBB4_4
+; CHECK-NEXT: # BB#2: # %bb1
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: movl %ecx, B
+; CHECK-NEXT: je .LBB4_3
+; CHECK-NEXT: .LBB4_4: # %bb3
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB4_3: # %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retl
; CHECK-CGP-LABEL: @and_sink5(
; CHECK-CGP: and i32
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