[llvm] r304347 - [TableGen] Adapt more places to getValueAsString now returning a StringRef instead of a std::string.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed May 31 14:12:47 PDT 2017
Author: ctopper
Date: Wed May 31 16:12:46 2017
New Revision: 304347
URL: http://llvm.org/viewvc/llvm-project?rev=304347&view=rev
Log:
[TableGen] Adapt more places to getValueAsString now returning a StringRef instead of a std::string.
Modified:
llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
llvm/trunk/utils/TableGen/Attributes.cpp
llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
llvm/trunk/utils/TableGen/SearchableTableEmitter.cpp
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp
Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed May 31 16:12:46 2017
@@ -354,11 +354,11 @@ public:
class AsmVariantInfo {
public:
- std::string RegisterPrefix;
- std::string TokenizingCharacters;
- std::string SeparatorCharacters;
- std::string BreakCharacters;
- std::string Name;
+ StringRef RegisterPrefix;
+ StringRef TokenizingCharacters;
+ StringRef SeparatorCharacters;
+ StringRef BreakCharacters;
+ StringRef Name;
int AsmVariantNo;
};
@@ -1438,8 +1438,8 @@ void AsmMatcherInfo::buildInfo() {
unsigned VariantCount = Target.getAsmParserVariantCount();
for (unsigned VC = 0; VC != VariantCount; ++VC) {
Record *AsmVariant = Target.getAsmParserVariant(VC);
- std::string CommentDelimiter =
- AsmVariant->getValueAsString("CommentDelimiter");
+ StringRef CommentDelimiter =
+ AsmVariant->getValueAsString("CommentDelimiter");
AsmVariantInfo Variant;
Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
Variant.TokenizingCharacters =
@@ -1463,7 +1463,7 @@ void AsmMatcherInfo::buildInfo() {
continue;
// Ignore instructions for different instructions
- const std::string V = CGI->TheDef->getValueAsString("AsmVariantName");
+ StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
if (!V.empty() && V != Variant.Name)
continue;
@@ -1495,7 +1495,7 @@ void AsmMatcherInfo::buildInfo() {
.startswith( MatchPrefix))
continue;
- const std::string V = Alias->TheDef->getValueAsString("AsmVariantName");
+ StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");
if (!V.empty() && V != Variant.Name)
continue;
@@ -1564,8 +1564,8 @@ void AsmMatcherInfo::buildInfo() {
// If the instruction has a two-operand alias, build up the
// matchable here. We'll add them in bulk at the end to avoid
// confusing this loop.
- std::string Constraint =
- II->TheDef->getValueAsString("TwoOperandAliasConstraint");
+ StringRef Constraint =
+ II->TheDef->getValueAsString("TwoOperandAliasConstraint");
if (Constraint != "") {
// Start by making a copy of the original matchable.
auto AliasII = llvm::make_unique<MatchableInfo>(*II);
@@ -1898,10 +1898,10 @@ static void emitConvertFuncs(CodeGenTarg
for (auto &II : Infos) {
// Check if we have a custom match function.
- std::string AsmMatchConverter =
- II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
+ StringRef AsmMatchConverter =
+ II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
- std::string Signature = "ConvertCustom_" + AsmMatchConverter;
+ std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
II->ConversionFnKind = Signature;
// Check if we have already generated this signature.
@@ -2443,7 +2443,7 @@ static void emitMnemonicAliasVariant(raw
for (Record *R : Aliases) {
// FIXME: Allow AssemblerVariantName to be a comma separated list.
- std::string AsmVariantName = R->getValueAsString("AsmVariantName");
+ StringRef AsmVariantName = R->getValueAsString("AsmVariantName");
if (AsmVariantName != AsmParserVariantName)
continue;
AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
@@ -2526,7 +2526,7 @@ static bool emitMnemonicAliases(raw_ostr
for (unsigned VC = 0; VC != VariantCount; ++VC) {
Record *AsmVariant = Target.getAsmParserVariant(VC);
int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
- std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
+ StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name");
OS << " case " << AsmParserVariantNo << ":\n";
emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
AsmParserVariantName);
@@ -2714,7 +2714,7 @@ static void emitCustomOperandParsing(raw
void AsmMatcherEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
Record *AsmParser = Target.getAsmParser();
- std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
+ StringRef ClassName = AsmParser->getValueAsString("AsmParserClassName");
// Compute the information on the instructions to match.
AsmMatcherInfo Info(AsmParser, Target, Records);
@@ -3177,8 +3177,7 @@ void AsmMatcherEmitter::run(raw_ostream
<< " }\n\n";
// Call the post-processing function, if used.
- std::string InsnCleanupFn =
- AsmParser->getValueAsString("AsmParserInstCleanup");
+ StringRef InsnCleanupFn = AsmParser->getValueAsString("AsmParserInstCleanup");
if (!InsnCleanupFn.empty())
OS << " " << InsnCleanupFn << "(Inst);\n";
Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Wed May 31 16:12:46 2017
@@ -272,7 +272,7 @@ static void UnescapeString(std::string &
/// clearing the Instructions vector.
void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
O <<
@@ -553,12 +553,11 @@ emitRegisterNameString(raw_ostream &O, S
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
const auto &Registers = Target.getRegBank().getRegisters();
const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices();
bool hasAltNames = AltNameIndices.size() > 1;
- std::string Namespace =
- Registers.front().TheDef->getValueAsString("Namespace");
+ StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
O <<
"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
@@ -583,14 +582,16 @@ void AsmWriterEmitter::EmitGetRegisterNa
O << " switch(AltIdx) {\n"
<< " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
for (const Record *R : AltNameIndices) {
- const std::string &AltName = R->getName();
- std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
- O << " case " << Prefix << AltName << ":\n"
- << " assert(*(AsmStrs" << AltName << "+RegAsmOffset"
- << AltName << "[RegNo-1]) &&\n"
+ StringRef AltName = R->getName();
+ O << " case ";
+ if (!Namespace.empty())
+ O << Namespace << "::";
+ O << AltName << ":\n"
+ << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
+ << "[RegNo-1]) &&\n"
<< " \"Invalid alt name index for register!\");\n"
- << " return AsmStrs" << AltName << "+RegAsmOffset"
- << AltName << "[RegNo-1];\n";
+ << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
+ << "[RegNo-1];\n";
}
O << " }\n";
} else {
@@ -762,7 +763,7 @@ void AsmWriterEmitter::EmitPrintAliasIns
//////////////////////////////
// Emit the method that prints the alias instruction.
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
unsigned Variant = AsmWriter->getValueAsInt("Variant");
bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
@@ -807,7 +808,7 @@ void AsmWriterEmitter::EmitPrintAliasIns
IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
- std::string Namespace = Target.getName();
+ StringRef Namespace = Target.getName();
std::vector<Record *> ReqFeatures;
if (PassSubtarget) {
// We only consider ReqFeatures predicates if PassSubtarget
@@ -845,7 +846,7 @@ void AsmWriterEmitter::EmitPrintAliasIns
// code to use.
if (Rec->isSubClassOf("RegisterOperand") ||
Rec->isSubClassOf("Operand")) {
- std::string PrintMethod = Rec->getValueAsString("PrintMethod");
+ StringRef PrintMethod = Rec->getValueAsString("PrintMethod");
if (PrintMethod != "" && PrintMethod != "printOperand") {
PrintMethodIdx =
llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin();
@@ -886,8 +887,9 @@ void AsmWriterEmitter::EmitPrintAliasIns
} else
break; // No conditions on this operand at all
}
- Cond = Target.getName().str() + ClassName + "ValidateMCOperand(" +
- Op + ", STI, " + utostr(Entry) + ")";
+ Cond = (Target.getName() + ClassName + "ValidateMCOperand(" + Op +
+ ", STI, " + utostr(Entry) + ")")
+ .str();
}
// for all subcases of ResultOperand::K_Record:
IAP.addCond(Cond);
@@ -923,7 +925,7 @@ void AsmWriterEmitter::EmitPrintAliasIns
for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) {
Record *R = *I;
- std::string AsmCondString = R->getValueAsString("AssemblerCondString");
+ StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
// AsmCondString has syntax [!]F(,[!]F)*
SmallVector<StringRef, 4> Ops;
@@ -933,10 +935,12 @@ void AsmWriterEmitter::EmitPrintAliasIns
for (auto &Op : Ops) {
assert(!Op.empty() && "Empty operator");
if (Op[0] == '!')
- Cond = "!STI.getFeatureBits()[" + Namespace + "::" +
- Op.substr(1).str() + "]";
+ Cond = ("!STI.getFeatureBits()[" + Namespace + "::" + Op.substr(1) +
+ "]")
+ .str();
else
- Cond = "STI.getFeatureBits()[" + Namespace + "::" + Op.str() + "]";
+ Cond =
+ ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str();
IAP.addCond(Cond);
}
}
Modified: llvm/trunk/utils/TableGen/Attributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Attributes.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Attributes.cpp (original)
+++ llvm/trunk/utils/TableGen/Attributes.cpp Wed May 31 16:12:46 2017
@@ -115,7 +115,7 @@ void Attributes::emitFnAttrCompatCheck(r
Records.getAllDerivedDefinitions("CompatRule");
for (auto *Rule : CompatRules) {
- std::string FuncName = Rule->getValueAsString("CompatFunc");
+ StringRef FuncName = Rule->getValueAsString("CompatFunc");
OS << " Ret &= " << FuncName << "(Caller, Callee);\n";
}
@@ -129,7 +129,7 @@ void Attributes::emitFnAttrCompatCheck(r
<< " const Function &Callee) {\n";
for (auto *Rule : MergeRules) {
- std::string FuncName = Rule->getValueAsString("MergeFunc");
+ StringRef FuncName = Rule->getValueAsString("MergeFunc");
OS << " " << FuncName << "(Caller, Callee);\n";
}
Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Wed May 31 16:12:46 2017
@@ -218,10 +218,12 @@ std::string CodeEmitterGen::getInstructi
AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
NamedOpIndices, Case, Target);
}
-
- std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
+
+ StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
if (!PostEmitter.empty()) {
- Case += " Value = " + PostEmitter + "(MI, Value";
+ Case += " Value = ";
+ Case += PostEmitter;
+ Case += "(MI, Value";
Case += ", STI";
Case += ");\n";
}
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed May 31 16:12:46 2017
@@ -2452,7 +2452,7 @@ void CodeGenDAGPatterns::ParseNodeTransf
while (!Xforms.empty()) {
Record *XFormNode = Xforms.back();
Record *SDNode = XFormNode->getValueAsDef("Opcode");
- std::string Code = XFormNode->getValueAsString("XFormFunction");
+ StringRef Code = XFormNode->getValueAsString("XFormFunction");
SDNodeXForms.insert(std::make_pair(XFormNode, NodeXForm(SDNode, Code)));
Xforms.pop_back();
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed May 31 16:12:46 2017
@@ -223,8 +223,8 @@ struct SDTypeConstraint {
/// processing.
class SDNodeInfo {
Record *Def;
- std::string EnumName;
- std::string SDClassName;
+ StringRef EnumName;
+ StringRef SDClassName;
unsigned Properties;
unsigned NumResults;
int NumOperands;
@@ -238,8 +238,8 @@ public:
/// variadic.
int getNumOperands() const { return NumOperands; }
Record *getRecord() const { return Def; }
- const std::string &getEnumName() const { return EnumName; }
- const std::string &getSDClassName() const { return SDClassName; }
+ StringRef getEnumName() const { return EnumName; }
+ StringRef getSDClassName() const { return SDClassName; }
const std::vector<SDTypeConstraint> &getTypeConstraints() const {
return TypeConstraints;
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Wed May 31 16:12:46 2017
@@ -542,7 +542,7 @@ void CodeGenSchedModels::collectSchedCla
return;
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
- std::string InstName = Inst->TheDef->getName();
+ StringRef InstName = Inst->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
if (!SCIdx) {
if (!Inst->hasNoSchedulingInfo)
Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed May 31 16:12:46 2017
@@ -1145,16 +1145,15 @@ bool FilterChooser::emitPredicateMatch(r
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;
- std::string P = Pred->getValueAsString("AssemblerCondString");
+ StringRef P = Pred->getValueAsString("AssemblerCondString");
- if (!P.length())
+ if (P.empty())
continue;
if (!IsFirstEmission)
o << " && ";
- StringRef SR(P);
- std::pair<StringRef, StringRef> pairs = SR.split(',');
+ std::pair<StringRef, StringRef> pairs = P.split(',');
while (!pairs.second.empty()) {
emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
o << " && ";
@@ -1174,9 +1173,9 @@ bool FilterChooser::doesOpcodeNeedPredic
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;
- std::string P = Pred->getValueAsString("AssemblerCondString");
+ StringRef P = Pred->getValueAsString("AssemblerCondString");
- if (!P.length())
+ if (P.empty())
continue;
return true;
@@ -1744,7 +1743,7 @@ static bool populateInstruction(CodeGenT
// If the instruction has specified a custom decoding hook, use that instead
// of trying to auto-generate the decoder.
- std::string InstDecoder = Def.getValueAsString("DecoderMethod");
+ StringRef InstDecoder = Def.getValueAsString("DecoderMethod");
if (InstDecoder != "") {
bool HasCompleteInstDecoder = Def.getValueAsBit("hasCompleteDecoder");
InsnOperands.push_back(OperandInfo(InstDecoder, HasCompleteInstDecoder));
@@ -2261,7 +2260,7 @@ void FixedLenDecoderEmitter::run(raw_ost
Def->getValueAsBit("isCodeGenOnly"))
continue;
- std::string DecoderNamespace = Def->getValueAsString("DecoderNamespace");
+ StringRef DecoderNamespace = Def->getValueAsString("DecoderNamespace");
if (Size) {
if (populateInstruction(Target, *Inst, i, Operands)) {
Modified: llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp Wed May 31 16:12:46 2017
@@ -44,7 +44,7 @@ public:
: TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
/// Get the human-readable name for the bank.
- std::string getName() const { return TheDef.getValueAsString("Name"); }
+ StringRef getName() const { return TheDef.getValueAsString("Name"); }
/// Get the name of the enumerator in the ID enumeration.
std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed May 31 16:12:46 2017
@@ -93,8 +93,7 @@ void RegisterInfoEmitter::runEnums(raw_o
// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
- std::string Namespace =
- Registers.front().TheDef->getValueAsString("Namespace");
+ StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
emitSourceFileHeader("Target Register Enum Values", OS);
@@ -354,7 +353,7 @@ void RegisterInfoEmitter::EmitRegMapping
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
- std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
+ StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
@@ -464,7 +463,7 @@ void RegisterInfoEmitter::EmitRegMapping
if (!maxLength)
return;
- std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
+ StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
// Emit reverse information about the dwarf register numbers.
for (unsigned j = 0; j < 2; ++j) {
Modified: llvm/trunk/utils/TableGen/SearchableTableEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SearchableTableEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SearchableTableEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SearchableTableEmitter.cpp Wed May 31 16:12:46 2017
@@ -112,8 +112,8 @@ private:
void SearchableTableEmitter::emitMappingEnum(std::vector<Record *> &Items,
Record *InstanceClass,
raw_ostream &OS) {
- std::string EnumNameField = InstanceClass->getValueAsString("EnumNameField");
- std::string EnumValueField;
+ StringRef EnumNameField = InstanceClass->getValueAsString("EnumNameField");
+ StringRef EnumValueField;
if (!InstanceClass->isValueUnset("EnumValueField"))
EnumValueField = InstanceClass->getValueAsString("EnumValueField");
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Wed May 31 16:12:46 2017
@@ -180,9 +180,9 @@ unsigned SubtargetEmitter::FeatureKeyVal
// Next feature
Record *Feature = FeatureList[i];
- const std::string &Name = Feature->getName();
- const std::string &CommandLineName = Feature->getValueAsString("Name");
- const std::string &Desc = Feature->getValueAsString("Desc");
+ StringRef Name = Feature->getName();
+ StringRef CommandLineName = Feature->getValueAsString("Name");
+ StringRef Desc = Feature->getValueAsString("Desc");
if (CommandLineName.empty()) continue;
@@ -237,7 +237,7 @@ unsigned SubtargetEmitter::CPUKeyValues(
// Next processor
Record *Processor = ProcessorList[i];
- const std::string &Name = Processor->getValueAsString("Name");
+ StringRef Name = Processor->getValueAsString("Name");
const std::vector<Record*> &FeatureList =
Processor->getValueAsListOfDefs("Features");
@@ -1212,7 +1212,7 @@ void SubtargetEmitter::EmitProcessorLook
// Next processor
Record *Processor = ProcessorList[i];
- const std::string &Name = Processor->getValueAsString("Name");
+ StringRef Name = Processor->getValueAsString("Name");
const std::string &ProcModelName =
SchedModels.getModelForProc(Processor).ModelName;
@@ -1360,9 +1360,9 @@ void SubtargetEmitter::ParseFeaturesFunc
for (Record *R : Features) {
// Next record
- const std::string &Instance = R->getName();
- const std::string &Value = R->getValueAsString("Value");
- const std::string &Attribute = R->getValueAsString("Attribute");
+ StringRef Instance = R->getName();
+ StringRef Value = R->getValueAsString("Value");
+ StringRef Attribute = R->getValueAsString("Attribute");
if (Value=="true" || Value=="false")
OS << " if (Bits[" << Target << "::"
Modified: llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp?rev=304347&r1=304346&r2=304347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp Wed May 31 16:12:46 2017
@@ -292,7 +292,7 @@ getMemOperandSize(const Record *MemRec,
(MemRec->getName() == "sdmem" || MemRec->getName() == "ssmem"))
return 128;
- std::string Name =
+ StringRef Name =
MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
if (Name == "Mem8")
return 8;
@@ -368,7 +368,7 @@ static inline const CodeGenInstruction *
getAltRegInst(const CodeGenInstruction *I, const RecordKeeper &Records,
const CodeGenTarget &Target) {
- std::string AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
+ StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
Record *AltRegInstRec = Records.getDef(AltRegInstStr);
assert(AltRegInstRec &&
"Alternative register form instruction def not found");
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