[llvm] r304284 - [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Wed May 31 01:27:46 2017
New Revision: 304284

URL: http://llvm.org/viewvc/llvm-project?rev=304284&view=rev
Log:
[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi

When generating code for a shift loop, check the shift
 amount against the literal value 0, not R0

Modified:
    llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp
    llvm/trunk/test/CodeGen/AVR/rot.ll

Modified: llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp?rev=304284&r1=304283&r2=304284&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp Wed May 31 01:27:46 2017
@@ -1500,9 +1500,9 @@ MachineBasicBlock *AVRTargetLowering::in
   unsigned DstReg = MI.getOperand(0).getReg();
 
   // BB:
-  // cp 0, N
+  // cpi N, 0
   // breq RemBB
-  BuildMI(BB, dl, TII.get(AVR::CPRdRr)).addReg(ShiftAmtSrcReg).addReg(AVR::R0);
+  BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
   BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
 
   // LoopBB:

Modified: llvm/trunk/test/CodeGen/AVR/rot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/rot.ll?rev=304284&r1=304283&r2=304284&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/rot.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/rot.ll Wed May 31 01:27:46 2017
@@ -6,7 +6,7 @@
 define i8 @rol8(i8 %val, i8 %amt) {
   ; CHECK:      andi r22, 7
 
-  ; CHECK-NEXT: cp r22, r0
+  ; CHECK-NEXT: cpi r22, 0
   ; CHECK-NEXT: breq LBB0_2
 
 ; CHECK-NEXT: LBB0_1:
@@ -32,7 +32,7 @@ define i8 @rol8(i8 %val, i8 %amt) {
 define i8 @ror8(i8 %val, i8 %amt) {
   ; CHECK:      andi r22, 7
 
-  ; CHECK-NEXT: cp r22, r0
+  ; CHECK-NEXT: cpi r22, 0
   ; CHECK-NEXT: breq LBB1_2
 
 ; CHECK-NEXT: LBB1_1: